Added XML patching for CFLS and CFLH platforms
This patch added support for CFLS and CFLH stitching by patching proper xml file for the platforms. Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
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9435382022
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@ -143,12 +143,10 @@ def get_xml_change_list (platform, spi_quad):
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('./FlashSettings/FlashConfiguration/QuadIoReadEnable', value),
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('./FlashSettings/FlashConfiguration/QuadOutReadEnable', value),
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#VsccTable
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('./FlashSettings/VsccTable/VsccEntries/VsccEntry/VsccEntryName', 'vscc_entry0'),
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('./FlashSettings/VsccTable/VsccEntries/VsccEntry/VsccEntryName', 'W25Q256FV'),
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('./FlashSettings/VsccTable/VsccEntries/VsccEntry/VsccEntryVendorId', '0xEF'),
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('./FlashSettings/VsccTable/VsccEntries/VsccEntry/VsccEntryDeviceId0', '0x40'),
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('./FlashSettings/VsccTable/VsccEntries/VsccEntry/VsccEntryDeviceId1', '0x19'),
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#IntelMekernel
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('./IntelMeKernel/Processor/ProcEmulation', 'EMULATE Intel (R) vPro (TM) capable Processor'),
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#PttConfiguration
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('./PlatformProtection/IntelPttConfiguration/PttSupported', 'No'),
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('./PlatformProtection/IntelPttConfiguration/PttPwrUpState', 'Disabled'),
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@ -158,21 +156,21 @@ def get_xml_change_list (platform, spi_quad):
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutCpunsscPnPath', 'Direct XTAL IN / Out Path'),
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#Networking
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('./NetworkingConnectivity/WiredLanConfiguration/PhyConnected', 'PHY on SMLink0'),
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#SMBUS
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('./InternalPchBuses/SmbusSmlinkConfiguration/SLink1freq', '1 MHz'),
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#ISH
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('./IntegratedSensorHub/IshSupported', 'No'),
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#CPU Straps
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('./CpuStraps/IaPowerPlaneTopology', '0x00000000'),
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('./CpuStraps/RingPowerPlaneTopology', '0x00000000'),
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('./CpuStraps/GtUsPowerPlaneTopology', '0x00000001'),
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('./CpuStraps/GtSPowerPlaneTopology', '0x00000001'),
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])
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if platform == 'whl':
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xml_change_list.append ([
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('./PlatformProtection/IntelPttConfiguration/PttSupportedFpf', 'No'),
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#IntelMekernel
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('./IntelMeKernel/Processor/ProcEmulation', 'EMULATE Intel (R) vPro (TM) capable Processor'),
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#StrapsDifferences
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#CPU Straps
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('./CpuStraps/IaPowerPlaneTopology', '0x00000000'),
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('./CpuStraps/RingPowerPlaneTopology', '0x00000000'),
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('./CpuStraps/GtUsPowerPlaneTopology', '0x00000001'),
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('./CpuStraps/GtSPowerPlaneTopology', '0x00000001'),
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('./StrapsDifferences/PCH_Strap_SPI_touch2_max_freq_Diff', '0x03'),
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('./StrapsDifferences/PCH_Strap_PN0_RPCFG_0_Diff', '0x03'),
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('./StrapsDifferences/PCH_Strap_PN1_RPCFG_0_Diff', '0x03'),
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@ -205,6 +203,45 @@ def get_xml_change_list (platform, spi_quad):
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('./Gpio/GpioVccioVoltageControl/GppH17voltSelect', '1.8Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH20voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH22voltSelect', '3.3Volts'),
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#SMBUS
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('./InternalPchBuses/SmbusSmlinkConfiguration/SLink1freq', '1 MHz'),
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])
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if platform == 'cflh':
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xml_change_list.append ([
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#Networking
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('./NetworkingConnectivity/WiredLanConfiguration/GbePCIePortSelect', 'Port 5'),
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('./InternalPchBuses/DmiConfiguration/DmiLaneReversal', 'No'),
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('./Debug/DirectConnectInterfaceConfiguration/Usb9DciBssbEnable', 'Yes'),
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('./CpuStraps/SaVrType', 'SVID'),
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('./CpuStraps/VccinSvidAddrs', '0x0'),
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('./CpuStraps/VccinVrType', 'SVID'),
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('./StrapsDifferences/PCH_Strap_PN1_RPCFG_2_Diff', '0x2'),
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('./StrapsDifferences/PCH_Strap_PN2_RPCFG_2_Diff', '0x2'),
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('./FlexIO/IntelRstForPcieConfiguration/RstPCIeController3', '2x2'),
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('./FlexIO/PcieLaneReversalConfiguration/PCIeCtrl3LnReversal', 'Yes'),
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('./FlexIO/PciePortConfiguration/PCIeContoller2Config', '4x1'),
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('./FlexIO/PciePortConfiguration/PCIeContoller5Config', '4x1'),
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('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort1', 'GPIO Polarity PCIe'),
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('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort2', 'Disabled'),
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('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort3', 'Disabled'),
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('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort6', 'SATA'),
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('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort7', 'SATA'),
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('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort8', 'SATA'),
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('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort9', 'SATA'),
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('./FlexIO/Usb3PortConfiguration/USB3PCIeComboPort2', 'USB3'),
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('./FlexIO/Usb3PortConfiguration/USB3Prt9ConTypeSel', 'Type A'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt9ConTypeSel', 'Type A'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt14ConTypeSel', 'Express Card / M.2 S2'),
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('./Gpio/MeFeaturePins/TouchResetGpio', 'GPP_B_14'),
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('./Gpio/MeFeaturePins/TouchIntGpio', 'GPP_D_15'),
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('./Gpio/GpioVccioVoltageControl/Clkout48ModeConfig', 'GPP_A16'),
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])
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if platform == 'cfls':
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xml_change_list.append ([
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#IntelMekernel
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('./IntelMeKernel/Processor/ProcEmulation', 'EMULATE Intel (R) vPro (TM) capable Processor'),
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])
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return xml_change_list
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@ -423,7 +460,7 @@ def gen_xml_file(stitch_dir, cfg_var, btg_profile, spi_quad, platform):
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if platform == 'whl':
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cmd = './fit -sku "CNP-LP Base U" -save new.xml'
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elif platform == 'cfls':
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cmd = './fit -sku Z390 -save new.xml'
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cmd = './fit -sku Q370 -save new.xml'
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elif platform == 'cflh':
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cmd = './fit -sku QM370 -save new.xml'
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run_cmd (cmd, os.path.join(stitch_dir, cfg_var['fitinput']))
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