Support different CPU sort method
Different use case might want to have a different CPU order. e.g. P-core first or E-core first. This patch adds an option to help user sort CPU. platform could add "self.CPU_SORT_METHOD = value" to BoardConfig.py to override the default value. Signed-off-by: Guo Dong <guo.dong@intel.com>
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@ -146,6 +146,10 @@
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gPlatformModuleTokenSpaceGuid.PcdSeedListBufferSize | 0x00000400 | UINT32 | 0x200000E2
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gPlatformModuleTokenSpaceGuid.PcdSmbiosTablesSize | 0x1000 | UINT16 | 0x200000E3
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# 0: Sort the CPU according to their thread distances
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# 1: Sort the CPU based on CPU APIC ID in ascending order
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# 2: Sort the CPU based on CPU APIC ID in descending order
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gPlatformModuleTokenSpaceGuid.PcdCpuSortMethod | 0 | UINT32 | 0x200000E4
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# Size of the Hash store allocated in bootloader
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gPlatformModuleTokenSpaceGuid.PcdHashStoreSize | 0x00000200 | UINT32 | 0x200000F1
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@ -230,6 +230,7 @@
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gPlatformModuleTokenSpaceGuid.PcdAcpiProcessorIdBase | $(ACPI_PROCESSOR_ID_BASE)
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gPlatformModuleTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | $(CPU_MAX_LOGICAL_PROCESSOR_NUMBER)
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gPlatformModuleTokenSpaceGuid.PcdCpuSortMethod | $(CPU_SORT_METHOD)
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gPlatformCommonLibTokenSpaceGuid.PcdConsoleInDeviceMask | $(CONSOLE_IN_DEVICE_MASK)
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gPlatformCommonLibTokenSpaceGuid.PcdConsoleOutDeviceMask | $(CONSOLE_OUT_DEVICE_MASK)
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@ -1,7 +1,7 @@
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/** @file
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MP init library implementation.
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Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -74,10 +74,11 @@ CompareCpuApicId (
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}
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/**
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Sort the CPU entry according to their thread distances
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Sort the CPU entry
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It is required to list CPU thread with further distance first so as to
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fully utilize unshared CPU resources.
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It sort the CPU by the PCD PcdCpuSortMethod. Sort CPU by APIC ID in ascending order could make the debug easy.
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Sort CPU by the APIC ID in descending order might be required by some special case.
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Sort CPU by their thread distances could help fully utilize unshared CPU resources.
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@param[in] SysCpuInfo Pointer to the ALL_CPU_INFO structure.
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@ -98,9 +99,21 @@ SortSysCpu (
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return;
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}
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// Sort by APIC ID first
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// Sort the CPU by APIC ID
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PerformQuickSort (SysCpuInfo->CpuInfo, SysCpuInfo->CpuCount, sizeof (CPU_INFO), CompareCpuApicId, &Temp);
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if (FixedPcdGet32 (PcdCpuSortMethod) == 2) {
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// Sort the CPU by CPU APIC ID in descending order
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for (Idx1 = 0; Idx1 < SysCpuInfo->CpuCount / 2; Idx1++) {
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CopyMem (&Temp, &SysCpuInfo->CpuInfo[Idx1], sizeof(CPU_INFO));
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CopyMem (&SysCpuInfo->CpuInfo[Idx1], &SysCpuInfo->CpuInfo[SysCpuInfo->CpuCount - Idx1 - 1], sizeof(CPU_INFO));
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CopyMem (&SysCpuInfo->CpuInfo[SysCpuInfo->CpuCount - Idx1 - 1], &Temp, sizeof(CPU_INFO));
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}
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}
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if (FixedPcdGet32 (PcdCpuSortMethod) == 0) {
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// Sort the CPU according to their thread distances
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// Keep a backup copy
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CopyMem (&OldSysCpuInfo, SysCpuInfo, sizeof (ALL_CPU_INFO));
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@ -118,6 +131,7 @@ SortSysCpu (
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}
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}
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}
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}
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/**
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Relocate SMM base for CPU
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@ -1,6 +1,6 @@
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## @file
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#
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# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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@ -54,6 +54,7 @@
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[FixedPcd]
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gPlatformModuleTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
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gPlatformModuleTokenSpaceGuid.PcdCpuSortMethod
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[Pcd]
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gPlatformModuleTokenSpaceGuid.PcdSmramTsegBase
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@ -186,6 +186,7 @@ class BaseBoard(object):
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self.BUILD_CSME_UPDATE_DRIVER = 0
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self.CPU_MAX_LOGICAL_PROCESSOR_NUMBER = 16
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self.CPU_SORT_METHOD = 0
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self.ACM_SIZE = 0
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self.DIAGNOSTICACM_SIZE = 0
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