From 82274c1567b6500ee82048bd20fd88c71af74e1d Mon Sep 17 00:00:00 2001 From: Sean McGinn Date: Mon, 15 Aug 2022 22:12:25 -0700 Subject: [PATCH] Add SBL Resiliency Support to ADL-N Signed-off-by: Sean McGinn --- .../FspsUpdUpdateLib/FspsUpdUpdateLib.c | 4 ++ .../FspsUpdUpdateLib/FspsUpdUpdateLib.inf | 2 + .../Stage1ABoardInitLib/Stage1ABoardInitLib.c | 3 +- .../Stage1ABoardInitLib.inf | 1 + .../Stage1BBoardInitLib/Stage1BBoardInitLib.c | 63 +++++++++---------- .../Stage1BBoardInitLib/Stage1BBoardInitLib.h | 3 +- .../Stage1BBoardInitLib.inf | 3 + .../Stage1ASocInitLib/Stage1ASocInitLib.c | 10 --- .../Stage1ASocInitLib/Stage1ASocInitLib.inf | 1 - 9 files changed, 42 insertions(+), 48 deletions(-) diff --git a/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.c b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.c index 44b6512a..467fa27b 100644 --- a/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.c +++ b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.c @@ -721,6 +721,10 @@ UpdateFspConfig ( FspsConfig->EnableTimedGpio1 = SiCfgData->EnableTimedGpio1; FspsConfig->PchPmSlpAMinAssert = SiCfgData->PchPmSlpAMinAssert; + if (PcdGetBool (PcdSblResiliencyEnabled)) { + FspsConfig->EnableTcoTimer = 0x1; + } + // UFS if (IsPchLp ()) { FspsConfig->UfsEnable[0] = SiCfgData->PchUfsEnable[0]; diff --git a/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.inf b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.inf index ad62af37..5a175632 100644 --- a/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.inf +++ b/Platform/AlderlakeBoardPkg/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.inf @@ -45,5 +45,7 @@ gPlatformCommonLibTokenSpaceGuid.PcdTccEnabled gPlatformModuleTokenSpaceGuid.PcdEnablePciePm gPlatformModuleTokenSpaceGuid.PcdFastBootEnabled + gPlatformModuleTokenSpaceGuid.PcdSblResiliencyEnabled + [FixedPcd] gPlatformAlderLakeTokenSpaceGuid.PcdAdlLpSupport diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c b/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c index c63d219b..4f74989a 100644 --- a/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c +++ b/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c @@ -22,6 +22,7 @@ #include #include #include +#include #define UCODE_REGION_BASE FixedPcdGet32(PcdUcodeBase) #define UCODE_REGION_SIZE FixedPcdGet32(PcdUcodeSize) @@ -142,7 +143,7 @@ BoardInit ( switch (InitPhase) { case PostTempRamInit: - DisableWatchDogTimer (); + InitTcoTimer (); EarlyPlatformDataCheck (); DebugPort = GetDebugPort (); diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.inf b/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.inf index 00c3eb90..4dea1841 100644 --- a/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.inf +++ b/Platform/AlderlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.inf @@ -44,6 +44,7 @@ GpioLib ConfigDataLib PchInfoLib + TcoTimerLib [Guids] diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c index e132a4a4..f24738e4 100644 --- a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c +++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c @@ -169,6 +169,9 @@ PlatformDeviceTableInitialize ( SetDeviceTable (PltDeviceTable); } + + // clear SmBus in use status as TCO timer reload causes it to be marked in use here + SmBusClearInUseStatus (); } VOID @@ -176,13 +179,9 @@ FwuTopSwapSetting ( IN FW_UPDATE_STATUS *pFwUpdStatus ) { - UINT32 Data32; - UINT32 TopSwapReg; - UINT32 P2sbBar; EFI_STATUS Status; UINT32 RsvdBase; UINT32 RsvdSize; - UINTN P2sbBase; if (pFwUpdStatus == NULL) { Status = GetComponentInfoByPartition (FLASH_MAP_SIG_BLRESERVED, FALSE, &RsvdBase, &RsvdSize); @@ -192,43 +191,28 @@ FwuTopSwapSetting ( pFwUpdStatus = (FW_UPDATE_STATUS *)(UINTN)RsvdBase; } - // - // Get Top swap register Bit0 in PCH Private Configuration Space. - // - P2sbBase = MM_PCI_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_LPC, 1, 0); // P2SB device base - - if (MmioRead16 (P2sbBase) == 0xFFFF) { - // - // unhide P2SB - // - MmioWrite8 (P2sbBase + 0xE1, 0); - DEBUG ((DEBUG_INFO, "P2sb is hidden, unhide it\n")); + // If in a recovery path, stay on current partition + if (PcdGetBool (PcdSblResiliencyEnabled) && + (GetFailedBootCount () >= PcdGet8 (PcdBootFailureThreshold) || + pFwUpdStatus->StateMachine == FW_UPDATE_SM_RECOVERY)) { + return; } - P2sbBar = MmioRead32 (P2sbBase + 0x10); - P2sbBar &= 0xFFFFFFF0; - ASSERT (P2sbBar != 0xFFFFFFF0); - - TopSwapReg = P2sbBar | ((PID_RTC_HOST) << 16) | (UINT16)(R_RTC_PCR_BUC); - Data32 = MmioRead32 (TopSwapReg); - DEBUG ((DEBUG_INFO, "TopSwapReg=0x%x\n", Data32)); if (pFwUpdStatus->StateMachine == FW_UPDATE_SM_PART_A) { - if (GetCurrentBootPartition() == 0) { - SetBootPartition(1); - ResetSystem(EfiResetCold); + if (GetCurrentBootPartition () == PrimaryPartition) { + SetBootPartition (BackupPartition); + ResetSystem (EfiResetCold); } } else if (pFwUpdStatus->StateMachine == FW_UPDATE_SM_PART_B) { - if (GetCurrentBootPartition() == 1) { - SetBootPartition(0); - ResetSystem(EfiResetCold); + if (GetCurrentBootPartition () == BackupPartition) { + SetBootPartition (PrimaryPartition); + ResetSystem (EfiResetCold); + } + } else { + if (GetCurrentBootPartition () == BackupPartition) { + SetBootPartition (PrimaryPartition); + ResetSystem (EfiResetCold); } - } - else{ - if (GetCurrentBootPartition() == 1) { - SetBootPartition(0); - ResetSystem(EfiResetCold); - } - DEBUG ((DEBUG_INFO, "Not in Firmware Update mode.\n")); } } @@ -243,6 +227,7 @@ FwuTopSwapSetting ( BOOLEAN IsFirmwareUpdate () { + // // Check if state machine is set to capsule processing mode. // @@ -257,6 +242,14 @@ IsFirmwareUpdate () return TRUE; } + // + // Check if we need to recover a failing partition. + // + if (PcdGetBool (PcdSblResiliencyEnabled) && + GetFailedBootCount () >= PcdGet8 (PcdBootFailureThreshold)) { + return TRUE; + } + return FALSE; } diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h index d075281b..15f25c94 100644 --- a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h +++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.h @@ -45,8 +45,8 @@ #include #include #include -#include #include +#include #include "GpioTableAdlSPreMem.h" #include "GpioTableAdlPPreMem.h" #include "GpioTableAdlNPreMem.h" @@ -56,6 +56,7 @@ #include #include #include +#include /** Initialize Variable. diff --git a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf index bd671838..0b96fc2b 100644 --- a/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf +++ b/Platform/AlderlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf @@ -63,6 +63,7 @@ WatchDogTimerLib FspmUpdUpdateLib SmbusLib + TopSwapLib [Guids] gFspNonVolatileStorageHobGuid @@ -79,6 +80,8 @@ gPlatformCommonLibTokenSpaceGuid.PcdMeasuredBootEnabled gPlatformCommonLibTokenSpaceGuid.PcdVerifiedBootEnabled gPlatformCommonLibTokenSpaceGuid.PcdTccEnabled + gPlatformModuleTokenSpaceGuid.PcdSblResiliencyEnabled + gPlatformModuleTokenSpaceGuid.PcdBootFailureThreshold [FixedPcd] gPlatformAlderLakeTokenSpaceGuid.PcdAdlLpSupport diff --git a/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.c b/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.c index 42d7f26d..9392b600 100644 --- a/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.c +++ b/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.c @@ -9,7 +9,6 @@ #include #include #include -#include /** Disable watch dog timer @@ -20,15 +19,6 @@ DisableWatchDogTimer ( VOID ) { - // - // Halt the TCO timer - // - IoOr16 (TCO_BASE_ADDRESS + R_TCO_IO_TCO1_CNT, B_TCO_IO_TCO1_CNT_TMR_HLT); - - // - // Clear the Second TO status bit - // - IoOr8 (TCO_BASE_ADDRESS + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO); } /** diff --git a/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.inf b/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.inf index 4911c7b5..ff377662 100644 --- a/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.inf +++ b/Silicon/AlderlakePkg/Library/Stage1ASocInitLib/Stage1ASocInitLib.inf @@ -26,7 +26,6 @@ MdePkg/MdePkg.dec BootloaderCorePkg/BootloaderCorePkg.dec Silicon/AlderlakePkg/AlderlakePkg.dec - Silicon/CommonSocPkg/CommonSocPkg.dec [LibraryClasses] BaseLib