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[CFL] Fix S3/S4 resume 

S4 resume sets PWRBTN_EN. And since SCI_EN is set to 0,
this situation will generate spurious SMI# once GblSmi
is enabled.

Also moving RestoreS3regs before ProcessAllLocks, as SMI_LOCK
setting will prevent enabling GblSmi on S3 resume path.

Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This commit is contained in:
Sai Talamudupula 2019-08-02 17:46:34 -07:00 committed by Maurice Ma
parent 9a77e00c63
commit 4e3fafe315
3 changed files with 20 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Platform/CoffeelakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
View File

@ -570,13 +570,18 @@ GetPlatformPowerState (
} }
} }
///
/// Clear Wake Status
/// Also clear the PWRBTN_EN, it causes SMI# otherwise (SCI_EN is 0)
///
IoWrite32 (ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_STS, ((UINT32)~B_ACPI_IO_PM1_EN_PWRBTN_EN & R_ACPI_IO_PM1_EN_MASK) | B_ACPI_IO_PM1_STS_WAK );
if ((MmioRead8 (PCH_PWRM_BASE_ADDRESS + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS) != 0) { if ((MmioRead8 (PCH_PWRM_BASE_ADDRESS + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS) != 0) {
BootMode = BOOT_WITH_FULL_CONFIGURATION; BootMode = BOOT_WITH_FULL_CONFIGURATION;
/// ///
/// Clear Wake Status and Sleep Type /// Clear Sleep Type
/// ///
IoWrite16 (ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_WAK);
IoAndThenOr16 (ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT, (UINT16) ~B_ACPI_IO_PM1_CNT_SLP_TYP, V_ACPI_IO_PM1_CNT_S0); IoAndThenOr16 (ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT, (UINT16) ~B_ACPI_IO_PM1_CNT_SLP_TYP, V_ACPI_IO_PM1_CNT_S0);
} }

16
Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -839,6 +839,7 @@ STATIC S3_SAVE_REG mS3SaveReg = {
{ { IO, WIDE32, { 0, 0}, (ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_EN), 0x00000000 } } { { IO, WIDE32, { 0, 0}, (ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_EN), 0x00000000 } }
}; };
/** /**
Initialize Board specific things in Stage2 Phase Initialize Board specific things in Stage2 Phase
@ -1000,7 +1001,17 @@ BoardInit (
} }
break; break;
case ReadyToBoot: case ReadyToBoot:
//
// Clear Smi and restore S3 regs on S3 resume
//
ClearSmi ();
if ((GetBootMode() == BOOT_ON_S3_RESUME) && (GetPayloadId () == UEFI_PAYLOAD_ID_SIGNATURE)) {
RestoreS3RegInfo (FindS3Info (S3_SAVE_REG_COMM_ID));
}
//
// Do necessary locks, and clean up before jumping tp OS
//
SiliconCfgData = (SILICON_CFG_DATA *)FindConfigDataByTag (CDATA_SILICON_TAG); SiliconCfgData = (SILICON_CFG_DATA *)FindConfigDataByTag (CDATA_SILICON_TAG);
if ( (SiliconCfgData != NULL) && (SiliconCfgData->ECEnable == 1)){ if ( (SiliconCfgData != NULL) && (SiliconCfgData->ECEnable == 1)){
// //
@ -1053,13 +1064,8 @@ BoardInit (
// //
TcoBase = MmioRead16(PCH_PCR_ADDRESS(PID_DMI, R_PCH_DMI_PCR_TCOBASE)) & B_PCH_DMI_PCR_TCOBASE_TCOBA; TcoBase = MmioRead16(PCH_PCR_ADDRESS(PID_DMI, R_PCH_DMI_PCR_TCOBASE)) & B_PCH_DMI_PCR_TCOBASE_TCOBA;
IoOr16 ((TcoBase + R_TCO_IO_TCO1_CNT), B_TCO_IO_TCO1_CNT_LOCK); IoOr16 ((TcoBase + R_TCO_IO_TCO1_CNT), B_TCO_IO_TCO1_CNT_LOCK);
break; break;
case EndOfFirmware: case EndOfFirmware:
ClearSmi ();
if ((GetBootMode() == BOOT_ON_S3_RESUME) && (GetPayloadId () == UEFI_PAYLOAD_ID_SIGNATURE)) {
RestoreS3RegInfo (FindS3Info (S3_SAVE_REG_COMM_ID));
}
break; break;
default: default:
break; break;

2
Silicon/CoffeelakePkg/Include/Register/PchRegsPmc.h
View File

@ -19,6 +19,8 @@
#define R_ACPI_IO_PM1_STS 0x00 #define R_ACPI_IO_PM1_STS 0x00
#define B_ACPI_IO_PM1_STS_WAK BIT15 #define B_ACPI_IO_PM1_STS_WAK BIT15
#define R_ACPI_IO_PM1_EN_MASK 0xFFFF0000
#define B_ACPI_IO_PM1_EN_PWRBTN_EN BIT24
#define R_ACPI_IO_PM1_CNT 0x04 #define R_ACPI_IO_PM1_CNT 0x04
#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) #define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)