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[EHL] Fsp Upd update (#1087) 

Changes of Fsp Upd below:
1. DAM
2. DciModphyPg and Trace hub
3. PchPse SPI and I2C

Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This commit is contained in:
koktong-ong 2021-04-01 04:09:01 +08:00 committed by GitHub
parent 81face39fb
commit 4cf45a8c64
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 7 additions and 10 deletions
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6
Platform/ElkhartlakeBoardPkg/CfgData/CfgData_Silicon.yaml
View File

@ -905,7 +905,7 @@
help : >
Set if PSE UART native pins and ownership are to be enabled by BIOS. 0- Disable/pins are not owned by PSE/host; 1- Pins are muxed to PSE IP, the IO is owned by PSE; 2- Pins are muxed to PSE IP, the IO is owned by host;
length : 0x06
value : { 0x00, 0x01, 0x01, 0x00, 0x00, 0x00 }
value : { 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 }
- PchPseHsuartEnable :
name : Enable PCH PSE HSUART pins assigned
type : EditNum, HEX, (0x0,0xFFFFFFFF)
@ -940,14 +940,14 @@
help : >
Set if PSE I2C native pins and ownership are to be enabled by BIOS. 0- Disable/pins are not owned by PSE/host; 1- Pins are muxed to PSE IP, the IO is owned by PSE; 2- Pins are muxed to PSE IP, the IO is owned by host;
length : 0x08
value : { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }
value : { 0x02, 0x02, 0x01, 0x00, 0x00, 0x00, 0x02, 0x01 }
- PchPseSpiEnable :
name : Enable PCH PSE SPI pins assigned
type : EditNum, HEX, (0x0,0xFFFFFFFF)
help : >
Set if PSE SPI native pins and ownership are to be enabled by BIOS. 0- Disable/pins are not owned by PSE/host; 1- Pins are muxed to PSE IP, the IO is owned by PSE; 2- Pins are muxed to PSE IP, the IO is owned by host;
length : 0x04
value : { 0x00, 0x00, 0x00, 0x00 }
value : { 0x02, 0x00, 0x00, 0x00 }
- PchPseSpiCs0Enable :
name : Enable PCH PSE SPI CS0 pins assigned
type : EditNum, HEX, (0x0,0xFFFFFFFF)

11
Platform/ElkhartlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
View File

@ -559,9 +559,10 @@ UpdateFspConfig (
break;
case ProbeTypeManual:
Fspmcfg->DciModphyPg = FALSE;
Fspmcfg->CpuTraceHubMode = 0x1;
Fspmcfg->PchTraceHubMode = 0x1;
Fspmcfg->DciModphyPg = 0x1;
Fspmcfg->DciDbcMode = 0x0;
Fspmcfg->CpuTraceHubMode = 0x0;
Fspmcfg->PchTraceHubMode = 0x0;
break;
default:
@ -859,11 +860,7 @@ PlatformFeaturesInit (
// Update platform specific feature from configuration data.
PlatformFeatures = &((PLATFORM_DATA *)GetPlatformDataPtr ())->PlatformFeatures;
if (PlatformFeatures != NULL) {
if (FeaturePcdGet (PcdPreOsCheckerEnabled) && PchIsSciSupported ()) {
PlatformFeatures->DebugConsent = 7;
} else {
PlatformFeatures->DebugConsent = FeaturesCfgData->Features.DebugConsent;
}
PlatformFeatures->TccMode = FeaturesCfgData->Features.Tcc;
PlatformFeatures->TcctBase = NULL;
PlatformFeatures->TcctSize = 0;