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[EHL] Update PROJ_MINOR_VER and PSE SIZE 

1. Update VERINFO_PROJ_MINOR_VER to 3 for MR3
2. Update PSE SIZE to 0x00030000
3. Removal of PchCpuTempSensorEnable FSP UPD due
FSP update

Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This commit is contained in:
Ong Kok Tong 2022-01-13 15:45:36 +08:00 committed by Maurice Ma
parent 7db4278f0f
commit 44faa431c9
2 changed files with 2 additions and 3 deletions
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4
Platform/ElkhartlakeBoardPkg/BoardConfig.py
View File

@ -26,7 +26,7 @@ class Board(BaseBoard):
# VERINFO_PROJ_MAJOR_VER: 1 PV Quality release
# VERINFO_PROJ_MINOR_VER: 0: PV 1: MR1 2: MR2 etc.
self.VERINFO_PROJ_MAJOR_VER = 1
self.VERINFO_PROJ_MINOR_VER = 2
self.VERINFO_PROJ_MINOR_VER = 3
self.VERINFO_SVN = 1
self.VERINFO_BUILD_DATE = time.strftime("%m/%d/%Y")
self.LOWEST_SUPPORTED_FW_VER = ((self.VERINFO_PROJ_MAJOR_VER << 8) + self.VERINFO_PROJ_MINOR_VER)
@ -82,7 +82,7 @@ class Board(BaseBoard):
self.ENABLE_PSEFW_LOADING = 0
if self.ENABLE_PSEFW_LOADING:
self.PSEF_SIZE = 0x00020000
self.PSEF_SIZE = 0x00030000
self.SIIPFW_SIZE += self.PSEF_SIZE
if self.ENABLE_TSN:

1
Platform/ElkhartlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -963,7 +963,6 @@ FspUpdatePsePolicy (
Fspscfg->PchPseLogOutputOffset = SiCfgData->PchPseLogOutputOffset;
Fspscfg->PchPseEcliteEnabled = 1;
Fspscfg->PchPseOobEnabled = 0;
Fspscfg->PchCpuTempSensorEnable = 1;
Fspscfg->PchPseWoLEnabled = 1;
//Fspscfg->PseJtagEnabled = 0;