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ARL: Update FSP-T UPD code region (#2257) 

The FSP UPD code region should try to cover SBL Stage1A and Stage1B
with a minimum region size. It would impact MTRR settings before memory
init and the MTRR settings would be updated after FspTempRamExit().

Reduce the code region size could improve boot performance for some
SKUs.

Signed-off-by: Guo Dong <guo.dong@intel.com>
This commit is contained in:
Guo Dong 2024-08-15 20:45:31 -07:00 committed by GitHub
parent e3dfb721bb
commit 13a07c93f5
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1 changed files with 2 additions and 2 deletions
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4
Platform/ArrowlakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.c
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@ -42,8 +42,8 @@
#define UCODE_REGION_BASE FixedPcdGet32(PcdUcodeBase)
#define UCODE_REGION_SIZE FixedPcdGet32(PcdUcodeSize)
#define SG1B_REDB_BASE (UINT32) ((2 * FixedPcdGet32(PcdTopSwapRegionSize)) + FixedPcdGet32(PcdRedundantRegionSize) + FixedPcdGet32(PcdStage1BSize))
#define CODE_REGION_SIZE ALIGN_UP (SG1B_REDB_BASE, SIZE_1MB)
#define CODE_REGION_SIZE FixedPcdGet32(PcdTopSwapRegionSize)
#define CODE_REGION_BASE (UINT32) (BASE_4GB - CODE_REGION_SIZE)
#define MTL_MAX_SERIALIO_UART_CONTROLLERS 3