[EHL] Disable s0ix feature (#1044)

Disable s0ix feature (fsp and fadt flag) until fix is ready.

Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This commit is contained in:
koktong-ong 2021-03-09 01:45:41 +08:00 committed by GitHub
parent a005a5772c
commit 12a0752e1e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 7 additions and 8 deletions

View File

@ -34,7 +34,7 @@
Platform/CommonBoardPkg/AcpiTables/Fpdt/Fpdt.aslc
Ssdt/SaSsdt.asl
SsdtRtd3/EhlCrbRtd3.asl
Lpit/Lpit.act
//Lpit/Lpit.act
Dmar/Dmar.aslc
CpuSsdt/Cpu0Cst.asl
CpuSsdt/Cpu0Hwp.asl

View File

@ -192,7 +192,7 @@ DefinitionBlock (
//Include ("PcieDock.asl")
Include ("PchRpPxsxWrapper.asl")
Include ("WifiDynamicSar.asl")
Include ("Pep.asl")
//Include ("Pep.asl")
Include ("Psm.asl")
Include ("Connectivity.asl")
Include ("MipiCamSensors.asl")

View File

@ -67,8 +67,7 @@
EFI_ACPI_6_1_RTC_S4 | \
EFI_ACPI_6_1_SLP_BUTTON | \
EFI_ACPI_6_1_PROC_C1 | \
EFI_ACPI_6_1_RESET_REG_SUP | \
EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE \
EFI_ACPI_6_1_RESET_REG_SUP \
)

View File

@ -220,9 +220,9 @@ External(WWAN_PCIE_ROOT_PORT.LASX)
Name(SCLK, 0)
Store(PS1C, SCLK)
Include("Rtd3Pcie.asl")
Scope(\_SB.PC00.RP01.PXSX) {
Include("Rtd3PcieSsdStorage.asl")
}
//Scope(\_SB.PC00.RP01.PXSX) {
//Include("Rtd3PcieSsdStorage.asl")
//}
}
///

View File

@ -671,7 +671,7 @@ PlatformUpdateAcpiGnvs (
PlatformNvs->ApicEnable = 1;
PlatformNvs->EcAvailable = 0;
PlatformNvs->LowPowerS0Idle = 1;
PlatformNvs->LowPowerS0Idle = 0;
PlatformNvs->TenSecondPowerButtonEnable = 8;