36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
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/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PLATFORM_BASE_H_
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#define _PLATFORM_BASE_H_
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#define ACPI_BASE_ADDRESS 0x500
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#define TCO_BASE_ADDRESS 0x400
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#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
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#define MAX_SOCKET 1
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#define MAX_IO_APICS 1
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#define MAX_IMC 2 // Maximum memory controllers per socket
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#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
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#define MAX_IIO_STACK 6
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#define IIO_STACK0 0
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#define IIO_STACK1 1
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#define IIO_STACK2 2
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#define IIO_STACK3 3
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#define IIO_STACK5 5
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#define MAX_LOGIC_IIO_STACK 8
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#define PCH_IOAPIC (1 << 0)
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#define PCH_IOAPIC_ID 0x08
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#define PCH_IOAPIC_ADDRESS 0xFEC00000
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#define HPET_BLOCK_ADDRESS 0xFED00000
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#define PCH_INTERRUPT_BASE 0
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#endif
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