46 lines
1.7 KiB
Python
46 lines
1.7 KiB
Python
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## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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sys.path.append(os.path.realpath(os.path.join(os.path.dirname (os.path.realpath(__file__)), '..', '..', '..', 'SblOpen', 'Platform', 'AlderlakeBoardPkg')))
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import BoardConfig as AlderlakeBoardConfig
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class Board(AlderlakeBoardConfig.Board):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_RPLPS'
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self.BOARD_NAME = 'rplps'
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 0
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self._CFGDATA_DEF_FILE = 'CfgDataDefRplp.yaml'
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self._EXTRA_INC_PATH = ['Silicon/RaptorlakePkg/Rplps/Fsp']
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self._FSP_PATH_NAME = 'Silicon/RaptorlakePkg/Rplps/Fsp'
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self.FSP_INF_FILE = 'Silicon/RaptorlakePkg/Rplps/Fsp/FspBinRplps.inf'
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self.BOARD_PKG_NAME_OVERRIDE = 'RaptorlakeBoardPkg'
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self.MICROCODE_INF_FILE = 'Silicon/RaptorlakePkg/Rplps/Microcode/MicrocodeRplps.inf'
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self._generated_cfg_file_prefix = ''
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self._CFGDATA_EXT_FILE = ['CfgDataInt_Rplps_Crb_Ddr5.dlt', 'CfgDataInt_Rplps_Rvp_Ddr5.dlt']
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self._MULTI_VBT_FILE = {1:'VbtRplPsRvp.dat', 2:'VbtRplPsCrb.dat'}
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self._LP_SUPPORT = True
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self.EPAYLOAD_SIZE = 0x230000
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# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
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self.DEBUG_PORT_NUMBER = 0x0
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self.FSP_M_STACK_TOP = 0xFEFDFF00
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self.PLD_HEAP_SIZE = 0x0C000000
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self.LOADER_RSVD_MEM_SIZE = 0x580000
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