109 lines
3.5 KiB
Diff
109 lines
3.5 KiB
Diff
From c0cef17a1ac568ddb4bf59d84875e969389166a4 Mon Sep 17 00:00:00 2001
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From: Ping Gao <ping.a.gao@intel.com>
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Date: Wed, 6 Sep 2017 16:13:40 +0800
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Subject: [PATCH 535/550] drm/i915/gvt: Simply the conformance check
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The overall comparison for non-context MMIOs only need once, then
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it's enough for conformance check that audit these MMIOs during
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runtime to make sure the value written to them are the same with
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the host cache. The way could void frequently overall comparion.
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Signed-off-by: Ping Gao <ping.a.gao@intel.com>
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Reviewed-by: Kevin Tian <kevin.tian@intel.com>
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Reviewed-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-on:
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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v2: rebase to 4.19, reuse gvt_host_reg() to fix wrong offset
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Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
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---
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drivers/gpu/drm/i915/gvt/cmd_parser.c | 26 ++++++++++++++++++++++++++
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drivers/gpu/drm/i915/gvt/gvt.h | 1 +
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drivers/gpu/drm/i915/gvt/mmio.c | 10 ++++++++++
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3 files changed, 37 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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index 9115c3dc2fc9..4fa37daf13d6 100644
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--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
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+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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@@ -966,6 +966,32 @@ static int cmd_handler_lri(struct parser_exec_state *s)
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ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
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if (ret)
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break;
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+
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+ if (s->vgpu->entire_nonctxmmio_checked
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+ && intel_gvt_mmio_is_non_context(gvt,
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+ cmd_reg(s, i))) {
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+ int offset = cmd_reg(s, i);
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+ int value = cmd_val(s, i + 1);
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+
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+ if (intel_gvt_mmio_has_mode_mask(gvt, offset)) {
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+ u32 mask = value >> 16;
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+
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+ vgpu_vreg(s->vgpu, offset) =
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+ (vgpu_vreg(s->vgpu, offset) & ~mask)
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+ | (value & mask);
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+ } else {
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+ vgpu_vreg(s->vgpu, offset) = value;
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+ }
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+
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+ if (gvt_host_reg(gvt, offset) !=
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+ vgpu_vreg(s->vgpu, offset)) {
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+
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+ gvt_err("vgpu%d unexpected non-context MMIO "
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+ "access by cmd 0x%x:0x%x,0x%x\n",
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+ s->vgpu->id, offset, value,
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+ gvt_host_reg(gvt, offset));
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+ }
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+ }
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}
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return ret;
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}
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
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index 882859c20332..7da1e9bad5cc 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.h
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+++ b/drivers/gpu/drm/i915/gvt/gvt.h
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@@ -239,6 +239,7 @@ struct intel_vgpu {
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unsigned long long *cached_guest_entry;
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bool ge_cache_enable;
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+ bool entire_nonctxmmio_checked;
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};
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/* validating GM healthy status*/
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diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
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index 4cb3f72ab56a..b6a974f55805 100644
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--- a/drivers/gpu/drm/i915/gvt/mmio.c
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+++ b/drivers/gpu/drm/i915/gvt/mmio.c
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@@ -213,6 +213,14 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
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if (ret < 0)
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goto err;
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+ if (vgpu->entire_nonctxmmio_checked
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+ && intel_gvt_mmio_is_non_context(vgpu->gvt, offset)
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+ && vgpu_vreg(vgpu, offset) != gvt_host_reg(gvt, offset)) {
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+ gvt_err("vgpu%d unexpected non-context MMIO change at 0x%x:0x%x,0x%x\n",
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+ vgpu->id, offset, vgpu_vreg(vgpu, offset),
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+ gvt_host_reg(gvt, offset));
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+ }
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+
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intel_gvt_mmio_set_accessed(gvt, offset);
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ret = 0;
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goto out;
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@@ -298,6 +306,8 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
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vgpu_vreg_t(vgpu, HUC_STATUS2) = I915_READ(HUC_STATUS2);
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mmio_hw_access_post(dev_priv);
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}
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+ /* Non-context MMIOs need entire check again if mmio/vgpu reset */
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+ vgpu->entire_nonctxmmio_checked = false;
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}
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/**
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--
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2.19.1
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