161 lines
5.6 KiB
Diff
161 lines
5.6 KiB
Diff
From 5f557103b870bbfe8399a1daa050cbdf36f1a8dd Mon Sep 17 00:00:00 2001
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From: Ping Gao <ping.a.gao@intel.com>
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Date: Wed, 30 Aug 2017 14:59:22 +0800
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Subject: [PATCH 530/550] drm/i915/gvt: Forbid command to access non-context
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registers
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After MMIO save/restore removing, the guest cannot access non-context
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registers through cmd. This patch implement it by replacing the
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target non-context register with a non-functional one in related
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commands.
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v2: 1. sort the non-context MMIO lists for searching friendly.
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2. add a new flag F_NON_CONTEXT, it help to do fast non-context
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MMIOs checking during runtime.
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v3: Mark non-context MMIOs by walk the array.
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v4: Define PVINFO page as a target scratch reg to redirect the cmd access.
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Signed-off-by: Ping Gao <ping.a.gao@intel.com>
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Reviewed-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-on:
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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v5: Rebase v4.19, fix conflict and reuse the code in
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6cef21a19649 - drm/i915/gvt: update vreg on inhibit context lri command
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410a63dd8ccf - drm/i915/gvt: Introduce non-context MMIO check routines
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and change mmio_attribute type to u16
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Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
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---
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drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 ++++++++
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drivers/gpu/drm/i915/gvt/gvt.h | 29 ++++++++++++++++++++++++-
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drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
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drivers/gpu/drm/i915/gvt/mmio_context.c | 2 ++
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drivers/gpu/drm/i915/i915_pvinfo.h | 6 +++++
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5 files changed, 46 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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index 8d130d4d58b7..729eb0f05f9f 100644
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--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
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+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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@@ -918,6 +918,15 @@ static int cmd_reg_handler(struct parser_exec_state *s,
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}
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}
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+ /* Re-direct the non-context MMIO access to VGT_SCRATCH_REG, it
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+ * has no functional impact to HW.
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+ */
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+ if (!strcmp(cmd, "lri") || !strcmp(cmd, "lrr-dst")
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+ || !strcmp(cmd, "lrm") || !strcmp(cmd, "pipe_ctrl")) {
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+ if (intel_gvt_mmio_is_non_context(gvt, offset))
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+ patch_value(s, cmd_ptr(s, index), VGT_SCRATCH_REG);
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+ }
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+
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/* TODO: Update the global mask if this MMIO is a masked-MMIO */
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intel_gvt_mmio_set_cmd_accessed(gvt, offset);
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return 0;
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
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index bbf2489f251d..68cc50f75803 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.h
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+++ b/drivers/gpu/drm/i915/gvt/gvt.h
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@@ -266,7 +266,7 @@ struct gvt_mmio_block {
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#define INTEL_GVT_MMIO_HASH_BITS 11
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struct intel_gvt_mmio {
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- u8 *mmio_attribute;
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+ u16 *mmio_attribute;
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/* Register contains RO bits */
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#define F_RO (1 << 0)
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/* Register contains graphics address */
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@@ -283,6 +283,8 @@ struct intel_gvt_mmio {
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#define F_UNALIGN (1 << 6)
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/* This reg is saved/restored in context */
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#define F_IN_CTX (1 << 7)
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+/* This reg is not in the context */
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+#define F_NON_CONTEXT (1 << 8)
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struct gvt_mmio_block *mmio_block;
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unsigned int num_mmio_block;
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@@ -719,6 +721,31 @@ static inline void intel_gvt_mmio_set_in_ctx(
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gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX;
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}
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+/**
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+ * intel_gvt_mmio_is_non_context - check a MMIO is non-context
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+ * @gvt: a GVT device
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+ * @offset: register offset
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+ *
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+ */
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+static inline bool intel_gvt_mmio_is_non_context(
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+ struct intel_gvt *gvt, unsigned int offset)
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+{
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+ return gvt->mmio.mmio_attribute[offset >> 2] & F_NON_CONTEXT;
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+}
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+
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+/**
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+ * intel_gvt_mmio_set_non_context - mark a MMIO is non-context
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+
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+ * @gvt: a GVT device
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+ * @offset: register offset
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+ *
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+ */
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+static inline void intel_gvt_mmio_set_non_context(
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+ struct intel_gvt *gvt, unsigned int offset)
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+{
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+ gvt->mmio.mmio_attribute[offset >> 2] |= F_NON_CONTEXT;
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+}
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+
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int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
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void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
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int intel_gvt_debugfs_init(struct intel_gvt *gvt);
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index 0fc1fb37e1ef..ce25433c6d77 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -92,7 +92,7 @@ static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
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}
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static int new_mmio_info(struct intel_gvt *gvt,
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- u32 offset, u8 flags, u32 size,
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+ u32 offset, u16 flags, u32 size,
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u32 addr_mask, u32 ro_mask, u32 device,
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gvt_mmio_func read, gvt_mmio_func write)
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{
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diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
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index e872f4847fbe..0221e87f34db 100644
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--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
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+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
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@@ -588,6 +588,8 @@ void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
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if (mmio->in_context) {
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gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
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intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
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+ } else {
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+ intel_gvt_mmio_set_non_context(gvt, mmio->reg.reg);
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}
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}
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}
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diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
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index c15d4578bb5f..fd26872f15b6 100644
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--- a/drivers/gpu/drm/i915/i915_pvinfo.h
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+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
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@@ -28,6 +28,12 @@
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#define VGT_PVINFO_PAGE 0x78000
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#define VGT_PVINFO_SIZE 0x1000
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+/* Scratch reg used for redirecting command access to registers, any
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+ * command access to PVINFO page would be discarded, so it has no HW
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+ * impact.
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+ */
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+#define VGT_SCRATCH_REG VGT_PVINFO_PAGE
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+
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/*
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* The following structure pages are defined in GEN MMIO space
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* for virtualization. (One page for now)
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--
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2.19.1
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