110 lines
3.9 KiB
Diff
110 lines
3.9 KiB
Diff
From 5980f3a40a357b561e2a6dc45ec5a5ddf1f5c078 Mon Sep 17 00:00:00 2001
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From: Zhipeng Gong <zhipeng.gong@intel.com>
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Date: Fri, 14 Sep 2018 16:10:22 +0800
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Subject: [PATCH 498/550] drm/i915/gvt: allocate ddb according to active pipes
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This patch add back the ddb allocation for the PLANE_CURSOR
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and allocate ddb according to current active pipes.
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In this way, this patch can support 4K monitors and fix the
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issue that cursor not work when enable_initial_modeset is 0.
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v2:
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- correct ddb start calculation
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Tracked-On: projectacrn/acrn-hypervisor#1171
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Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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Reviewed-by: Fei Jiang <fei.jiang@intel.com>
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---
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drivers/gpu/drm/i915/gvt/gvt.c | 16 ++++++++++------
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drivers/gpu/drm/i915/gvt/gvt.h | 2 ++
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drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++--
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3 files changed, 23 insertions(+), 8 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
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index e4a3823e1226..940443f08dfd 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.c
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+++ b/drivers/gpu/drm/i915/gvt/gvt.c
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@@ -317,22 +317,27 @@ void intel_gvt_init_pipe_info(struct intel_gvt *gvt);
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* plane information of DomU's planes, so here we statically allocate the
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* ddb entries for all the possible enabled planes.
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*/
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-static void intel_gvt_init_ddb(struct intel_gvt *gvt)
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+void intel_gvt_allocate_ddb(struct intel_gvt *gvt,
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+ struct skl_ddb_allocation *ddb, unsigned int active_crtcs)
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{
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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- struct skl_ddb_allocation *ddb = &gvt->ddb;
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unsigned int pipe_size, ddb_size, plane_size, plane_cnt;
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u16 start, end;
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enum pipe pipe;
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enum plane_id plane;
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+ int i = 0;
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+ int num_active = hweight32(active_crtcs);
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+
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+ if (!num_active)
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+ return;
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ddb_size = INTEL_INFO(dev_priv)->ddb_size;
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ddb_size -= 4; /* 4 blocks for bypass path allocation */
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- pipe_size = ddb_size / INTEL_INFO(dev_priv)->num_pipes;
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+ pipe_size = ddb_size / num_active;
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memset(ddb, 0, sizeof(*ddb));
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- for_each_pipe(dev_priv, pipe) {
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- start = pipe * ddb_size / INTEL_INFO(dev_priv)->num_pipes;
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+ for_each_pipe_masked(dev_priv, pipe, active_crtcs) {
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+ start = pipe_size * (i++);
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end = start + pipe_size;
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ddb->plane[pipe][PLANE_CURSOR].start = end - 8;
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ddb->plane[pipe][PLANE_CURSOR].end = end;
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@@ -470,7 +475,6 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
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}
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intel_gvt_init_pipe_info(gvt);
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- intel_gvt_init_ddb(gvt);
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ret = intel_gvt_hypervisor_host_init(&dev_priv->drm.pdev->dev, gvt,
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&intel_gvt_ops);
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
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index 9344293ed692..f4d9056175ae 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.h
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+++ b/drivers/gpu/drm/i915/gvt/gvt.h
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@@ -608,6 +608,8 @@ struct intel_gvt_ops {
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};
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int gvt_dom0_ready(struct drm_i915_private *dev_priv);
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+void intel_gvt_allocate_ddb(struct intel_gvt *gvt,
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+ struct skl_ddb_allocation *ddb, unsigned int active_crtcs);
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enum {
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GVT_FAILSAFE_UNSUPPORTED_GUEST,
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index affd3e821687..c7c7b5e78330 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -5212,9 +5212,18 @@ skl_compute_ddb(struct drm_atomic_state *state)
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memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
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#if IS_ENABLED(CONFIG_DRM_I915_GVT)
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- /* In GVT environemnt, we only use the statically allocated ddb */
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+ /*
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+ * In GVT environemnt, allocate ddb for all planes in active crtc.
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+ * When there is active pipe change, intel_state active_crtcs is
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+ * not zero and updated before dev_priv, so use intel_state
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+ * active_crtc when it is not zero.
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+ */
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if (dev_priv->gvt) {
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- memcpy(ddb, &dev_priv->gvt->ddb, sizeof(*ddb));
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+ unsigned int active_crtcs;
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+
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+ active_crtcs = intel_state->active_crtcs ?
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+ intel_state->active_crtcs : dev_priv->active_crtcs;
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+ intel_gvt_allocate_ddb(dev_priv->gvt, ddb, active_crtcs);
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return 0;
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}
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#endif
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--
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2.19.1
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