66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
From 5853f7d7456b8fc8d5efc3cb8f672f72e1790387 Mon Sep 17 00:00:00 2001
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From: Fei Jiang <fei.jiang@intel.com>
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Date: Fri, 14 Sep 2018 16:10:21 +0800
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Subject: [PATCH 492/550] drm/i915/gvt: handling pvmmio update of plane wm
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registers in GVT-g
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When pvmmio level PVMMIO_PLANE_WM_UPDATE is enabled, need handle multiple
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plane wm related registers updating when PLANE_NV12_BUF_CFG writing is
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traped.
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sos only patch.
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Signed-off-by: Fei Jiang <fei.jiang@intel.com>
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Reviewed-by: Min He <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/gvt/handlers.c | 26 +++++++++++++++++++++++++-
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1 file changed, 25 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index d1870e0a97f4..16e2d41174bd 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -2947,6 +2947,29 @@ static int skl_plane_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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return 0;
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}
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+static int pv_plane_wm_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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+ void *p_data, unsigned int bytes)
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+{
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+ unsigned int pipe = SKL_PLANE_REG_TO_PIPE(offset);
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+ unsigned int plane = SKL_PLANE_REG_TO_PLANE(offset);
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+ struct pv_plane_wm_update *pv_plane_wm =
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+ &vgpu->mmio.shared_page->pv_plane_wm;
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+ int level;
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+
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+ if (VGPU_PVMMIO(vgpu) & PVMMIO_PLANE_WM_UPDATE) {
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+ for (level = 0; level <= pv_plane_wm->max_wm_level; level++)
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(
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+ PLANE_WM(pipe, plane, level)),
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+ &pv_plane_wm->plane_wm_level[level], 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_WM_TRANS(pipe, plane)),
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+ &pv_plane_wm->plane_trans_wm_level, 4);
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+ /* null function for PLANE_BUF_CFG and PLANE_NV12_BUF_CFG */
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+ }
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+ return 0;
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+}
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+
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#define MMIO_PIPES_SDH(prefix, plane, s, d, r, w) do { \
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int pipe; \
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for_each_pipe(dev_priv, pipe) \
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@@ -3091,7 +3114,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
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MMIO_PLANES_SDH(PLANE_WM_BASE, 4 * 8, D_SKL_PLUS, NULL, skl_plane_mmio_write);
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MMIO_PLANES_DH(PLANE_WM_TRANS, D_SKL_PLUS, NULL, skl_plane_mmio_write);
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- MMIO_PLANES_DH(PLANE_NV12_BUF_CFG, D_SKL_PLUS, NULL, NULL);
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+ MMIO_PLANES_DH(PLANE_NV12_BUF_CFG, D_SKL_PLUS, NULL,
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+ pv_plane_wm_mmio_write);
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MMIO_PLANES_DH(PLANE_BUF_CFG, D_SKL_PLUS, NULL, NULL);
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MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
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--
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2.19.1
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