96 lines
3.4 KiB
Diff
96 lines
3.4 KiB
Diff
From f0a16826bcc7219b8ba2f5100958f5a739208c32 Mon Sep 17 00:00:00 2001
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From: Min He <min.he@intel.com>
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Date: Fri, 14 Sep 2018 16:10:17 +0800
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Subject: [PATCH 456/550] drm/i915/gvt: emit shadow ppgtt root in LRI
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Usually the PDP/PML4 root poiners should be updated through the context,
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however, on BXT, we found that sometimes the PDP/PML4 root pointers will
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be reverted back to an old value, which causes GPU hang. The reason is
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still unclear, but by adding LRI command in the ring buffer, we are able
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to update the PDP/PML4 root pointers successfully.
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So far we will treat this patch as a workaround, unless we figure out
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why the PDP/PML4 root pointers was reverted back.
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Change-Id: Id65f7621ed9d45073f220fd2d91112558e7820d9
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Signed-off-by: Min He <min.he@intel.com>
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Reviewed-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/gvt/cmd_parser.c | 27 +++++++++++++++++++++++++++
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drivers/gpu/drm/i915/gvt/cmd_parser.h | 1 +
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drivers/gpu/drm/i915/gvt/scheduler.c | 8 ++++++++
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3 files changed, 36 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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index a614db310ea2..95244b2cb679 100644
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--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
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+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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@@ -2710,6 +2710,33 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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return ret;
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}
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+#define GEN8_PDPES 4
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+int gvt_emit_pdps(struct intel_vgpu_workload *workload)
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+{
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+ const int num_cmds = GEN8_PDPES * 2;
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+ struct i915_request *req = workload->req;
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+ struct intel_engine_cs *engine = req->engine;
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+ u32 *cs;
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+ u32 *pdps = (u32 *)(workload->shadow_mm->ppgtt_mm.shadow_pdps);
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+ int i;
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+
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+ cs = intel_ring_begin(req, num_cmds * 2 + 2);
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+ if (IS_ERR(cs))
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+ return PTR_ERR(cs);
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+
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+ *cs++ = MI_LOAD_REGISTER_IMM(num_cmds);
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+ for (i = 0; i < GEN8_PDPES; i++) {
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+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
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+ *cs++ = pdps[i * 2];
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+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
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+ *cs++ = pdps[i * 2 + 1];
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+ }
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+ *cs++ = MI_NOOP;
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+ intel_ring_advance(req, cs);
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+
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+ return 0;
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+}
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+
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static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.h b/drivers/gpu/drm/i915/gvt/cmd_parser.h
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index 286703643002..1356803a0586 100644
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--- a/drivers/gpu/drm/i915/gvt/cmd_parser.h
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+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.h
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@@ -46,4 +46,5 @@ int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload);
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int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
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+int gvt_emit_pdps(struct intel_vgpu_workload *workload);
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#endif
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diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
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index 9d8f0bfc434c..7243324cb93c 100644
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--- a/drivers/gpu/drm/i915/gvt/scheduler.c
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+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
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@@ -619,6 +619,14 @@ static int prepare_workload(struct intel_vgpu_workload *workload)
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goto err_unpin_mm;
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}
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+ /* we consider this as an workaround to avoid the situation that
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+ * PDP's not updated, and right now we only limit it to BXT platform
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+ * since it's not reported on the other platforms
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+ */
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+ if (IS_BROXTON(vgpu->gvt->dev_priv)) {
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+ gvt_emit_pdps(workload);
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+ }
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+
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ret = copy_workload_to_ring_buffer(workload);
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if (ret) {
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gvt_vgpu_err("fail to generate request\n");
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--
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2.19.1
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