106 lines
3.7 KiB
Diff
106 lines
3.7 KiB
Diff
From b27cf4bdf6fd4e65e4e9e51a8c5cb6ede2a25b40 Mon Sep 17 00:00:00 2001
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From: Fei Jiang <fei.jiang@intel.com>
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Date: Fri, 14 Sep 2018 16:10:20 +0800
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Subject: [PATCH 624/743] drm/i915/gvt: handling pvmmio update of plane
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registers in GVT-g
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When pvmmio level PVMMIO_PLANE_UPDATE is enabled, need handle multiple
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plane related registers updating together when PLANE_SURF is traped.
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sos only patch.
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V2: restore sequence of skl_plane_mmio_write/skl_plane_mmio_write and
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skl_plane_surf_write, while need add extra declarations.
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Signed-off-by: Fei Jiang <fei.jiang@intel.com>
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Reviewed-by: Min He <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/gvt/handlers.c | 64 +++++++++++++++++++++++++++++
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1 file changed, 64 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index 14a75c6dff4d..afa15c0bb347 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -778,6 +778,66 @@ static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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return 0;
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}
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+static int skl_plane_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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+ void *p_data, unsigned int bytes);
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+static int skl_ps_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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+ void *p_data, unsigned int bytes);
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+
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+static void pvmmio_update_plane_register(struct intel_vgpu *vgpu,
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+ unsigned int pipe, unsigned int plane)
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+{
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+ struct pv_plane_update *pv_plane = &vgpu->mmio.shared_page->pv_plane;
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+
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+ /* null function for PLANE_COLOR_CTL, PLANE_AUX_DIST, PLANE_AUX_OFFSET,
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+ * and SKL_PS_PWR_GATE register trap
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+ */
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+
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+ if (pv_plane->flags & PLANE_KEY_BIT) {
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_KEYVAL(pipe, plane)),
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+ &pv_plane->plane_key_val, 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_KEYMAX(pipe, plane)),
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+ &pv_plane->plane_key_max, 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_KEYMSK(pipe, plane)),
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+ &pv_plane->plane_key_msk, 4);
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+ }
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_OFFSET(pipe, plane)),
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+ &pv_plane->plane_offset, 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_STRIDE(pipe, plane)),
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+ &pv_plane->plane_stride, 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_SIZE(pipe, plane)),
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+ &pv_plane->plane_size, 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_AUX_DIST(pipe, plane)),
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+ &pv_plane->plane_aux_dist, 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_AUX_OFFSET(pipe, plane)),
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+ &pv_plane->plane_aux_offset, 4);
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+
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+ if (pv_plane->flags & PLANE_SCALER_BIT) {
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+ skl_ps_mmio_write(vgpu,
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+ i915_mmio_reg_offset(SKL_PS_CTRL(pipe, plane)),
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+ &pv_plane->ps_ctrl, 4);
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+ skl_ps_mmio_write(vgpu,
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+ i915_mmio_reg_offset(SKL_PS_WIN_POS(pipe, plane)),
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+ &pv_plane->ps_win_ps, 4);
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+ skl_ps_mmio_write(vgpu,
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+ i915_mmio_reg_offset(SKL_PS_WIN_SZ(pipe, plane)),
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+ &pv_plane->ps_win_sz, 4);
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+ }
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_POS(pipe, plane)),
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+ &pv_plane->plane_pos, 4);
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+ skl_plane_mmio_write(vgpu,
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+ i915_mmio_reg_offset(PLANE_CTL(pipe, plane)),
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+ &pv_plane->plane_ctl, 4);
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+}
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+
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static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
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unsigned int reg)
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{
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@@ -2850,6 +2910,10 @@ static int skl_plane_surf_write(struct intel_vgpu *vgpu, unsigned int offset,
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i915_reg_t reg_1ac = _MMIO(_REG_701AC(pipe, plane));
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int flip_event = SKL_FLIP_EVENT(pipe, plane);
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+ /* plane disable is not pv and it is indicated by value 0 */
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+ if (*(u32 *)p_data != 0 && VGPU_PVMMIO(vgpu) & PVMMIO_PLANE_UPDATE)
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+ pvmmio_update_plane_register(vgpu, pipe, plane);
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+
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write_vreg(vgpu, offset, p_data, bytes);
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vgpu_vreg_t(vgpu, reg_1ac) = vgpu_vreg(vgpu, offset);
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--
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2.19.2
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