102 lines
3.5 KiB
Diff
102 lines
3.5 KiB
Diff
From af0b9444c11efa03c99f566f66f3101a0e2900f7 Mon Sep 17 00:00:00 2001
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From: Pei Zhang <pei.zhang@intel.com>
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Date: Fri, 14 Sep 2018 16:10:19 +0800
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Subject: [PATCH 617/743] drm/i915/gvt: get ready of memory for pvmmio
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To enable pvmmio feature, we need to prepare to regions memory: the mmio
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memory whose size is 2M for Gen8/9, and the 4K shared page. GVT creates
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them for every vGPU instance, guest i915 driver will map them to virtual
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address.
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Change-Id: Ifcbd0e55783e19125e98036622cd5d08624d34fa
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Signed-off-by: Pei Zhang <pei.zhang@intel.com>
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Acknowledged-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-on:
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/gvt/gvt.c | 2 ++
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drivers/gpu/drm/i915/gvt/gvt.h | 2 ++
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drivers/gpu/drm/i915/gvt/mmio.c | 22 ++++++++++++++++++----
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3 files changed, 22 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
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index 6261af450ee4..e4a3823e1226 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.c
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+++ b/drivers/gpu/drm/i915/gvt/gvt.c
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@@ -248,6 +248,8 @@ static void init_device_info(struct intel_gvt *gvt)
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info->max_support_vgpus = 8;
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info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
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info->mmio_size = 2 * 1024 * 1024;
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+ /* order of mmio size. assert(2^order == mmio_size) */
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+ info->mmio_size_order = 9;
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info->mmio_bar = 0;
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info->gtt_start_offset = 8 * 1024 * 1024;
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info->gtt_entry_size = 8;
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
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index 64139240207f..ba88f722d602 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.h
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+++ b/drivers/gpu/drm/i915/gvt/gvt.h
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@@ -71,6 +71,7 @@ struct intel_gvt_device_info {
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u32 max_support_vgpus;
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u32 cfg_space_size;
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u32 mmio_size;
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+ u32 mmio_size_order;
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u32 mmio_bar;
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unsigned long msi_cap_offset;
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u32 gtt_start_offset;
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@@ -100,6 +101,7 @@ struct intel_vgpu_fence {
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struct intel_vgpu_mmio {
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void *vreg;
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void *sreg;
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+ struct gvt_shared_page *shared_page;
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};
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#define INTEL_GVT_MAX_BAR_NUM 4
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diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
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index 878a8a1f5ff5..4cb3f72ab56a 100644
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--- a/drivers/gpu/drm/i915/gvt/mmio.c
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+++ b/drivers/gpu/drm/i915/gvt/mmio.c
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@@ -311,11 +311,21 @@ int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
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{
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const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
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- vgpu->mmio.vreg = vzalloc(array_size(info->mmio_size, 2));
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+ BUILD_BUG_ON(sizeof(struct gvt_shared_page) != PAGE_SIZE);
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+
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+ vgpu->mmio.sreg = vzalloc(info->mmio_size);
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+ vgpu->mmio.vreg = (void *)__get_free_pages(GFP_KERNEL,
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+ info->mmio_size_order);
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if (!vgpu->mmio.vreg)
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return -ENOMEM;
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- vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
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+ vgpu->mmio.shared_page = (struct gvt_shared_page *) __get_free_pages(
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+ GFP_KERNEL, 0);
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+ if (!vgpu->mmio.shared_page) {
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+ vfree(vgpu->mmio.vreg);
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+ vgpu->mmio.vreg = NULL;
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+ return -ENOMEM;
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+ }
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intel_vgpu_reset_mmio(vgpu, true);
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@@ -329,6 +339,10 @@ int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
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*/
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void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
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{
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- vfree(vgpu->mmio.vreg);
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- vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;
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+ const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
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+
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+ vfree(vgpu->mmio.sreg);
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+ free_pages((unsigned long) vgpu->mmio.vreg, info->mmio_size_order);
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+ free_pages((unsigned long) vgpu->mmio.shared_page, 0);
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+ vgpu->mmio.vreg = vgpu->mmio.sreg = vgpu->mmio.shared_page = NULL;
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}
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--
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2.19.2
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