158 lines
5.4 KiB
Diff
158 lines
5.4 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Brahim Abes <brahimx.abes@intel.com>
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Date: Fri, 14 Sep 2018 16:10:18 +0800
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Subject: [PATCH] drm/i915/gvt: Add new trace point to output per domain info
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Added trace point "i915_gem_request_add_domain" that prints the following
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extra fields per each packet:
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-is_shadow_ctx: Check for Dom0 or guest domains
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-hw_id: To check against i915_context_status's HW context id
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-vgt_id: The host or guests domain ID
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-pid: Process ID submitting the request
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Change-Id: I3a71e1d5909260df5a07c98291ee9e908f698ea2
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Signed-off-by: Brahim Abes <brahimx.abes@intel.com>
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Reviewed-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-on:
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/i915_debugfs.c | 30 ++++++++++++++++++
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drivers/gpu/drm/i915/i915_request.c | 1 +
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drivers/gpu/drm/i915/i915_trace.h | 47 +++++++++++++++++++++++++++++
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drivers/gpu/drm/i915/intel_drv.h | 5 +++
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4 files changed, 83 insertions(+)
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diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
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index f575aff..ff6d2c8 100644
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--- a/drivers/gpu/drm/i915/i915_debugfs.c
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+++ b/drivers/gpu/drm/i915/i915_debugfs.c
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@@ -1939,6 +1939,36 @@ static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
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ring->space, ring->head, ring->tail, ring->emit);
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}
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+bool is_shadow_context(struct i915_gem_context *ctx)
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+{
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+ if (ctx->name && !strncmp(ctx->name, "Shadow Context", 14))
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+ return true;
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+
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+ return false;
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+}
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+
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+int get_vgt_id(struct i915_gem_context *ctx)
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+{
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+ int vgt_id;
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+
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+ vgt_id = 0;
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+
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+ if (is_shadow_context(ctx))
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+ sscanf(ctx->name, "Shadow Context %d", &vgt_id);
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+
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+ return vgt_id;
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+}
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+
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+int get_pid_shadowed(struct i915_gem_context *ctx,
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+ struct intel_engine_cs *engine)
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+{
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+ int pid, vgt_id;
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+
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+ sscanf(ctx->name, "Shadow Context %d", &vgt_id);
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+ pid = intel_read_status_page(engine, I915_GEM_HWS_PID_INDEX + vgt_id);
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+ return pid;
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+}
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+
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static void describe_ctx_ring_shadowed(struct seq_file *m,
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struct i915_gem_context *ctx, struct intel_ring *ring,
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struct intel_engine_cs *engine)
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diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
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index 5c2c93c..1bd2a7e 100644
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--- a/drivers/gpu/drm/i915/i915_request.c
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+++ b/drivers/gpu/drm/i915/i915_request.c
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@@ -1054,6 +1054,7 @@ void i915_request_add(struct i915_request *request)
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lockdep_assert_held(&request->i915->drm.struct_mutex);
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trace_i915_request_add(request);
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+ trace_i915_request_add_domain(request);
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/*
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* Make sure that no request gazumped us - if it was allocated after
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diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
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index b50c6b8..af592e3 100644
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--- a/drivers/gpu/drm/i915/i915_trace.h
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+++ b/drivers/gpu/drm/i915/i915_trace.h
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@@ -679,6 +679,53 @@ DEFINE_EVENT(i915_request, i915_request_add,
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TP_ARGS(rq)
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);
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+TRACE_EVENT(i915_multi_domains,
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+ TP_PROTO(struct i915_request *req),
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+ TP_ARGS(req),
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+
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+ TP_STRUCT__entry(
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+ __field(u32, dev)
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+ __field(u32, ctx)
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+ __field(u32, ring)
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+ __field(u32, seqno)
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+ __field(u32, global)
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+ __field(int, prio_req)
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+ __field(int, prio_ctx)
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+ __field(bool, shadow_ctx)
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+ __field(u32, hw_id)
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+ __field(int, vgt_id)
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+ __field(u32, pid)
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+ ),
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+
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+ TP_fast_assign(
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+ __entry->dev = req->i915->drm.primary->index;
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+ __entry->ring = req->engine->id;
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+ __entry->ctx = req->fence.context;
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+ __entry->seqno = req->fence.seqno;
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+ __entry->global = req->global_seqno;
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+ __entry->prio_req = req->sched.attr.priority;
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+ __entry->prio_ctx = req->sched.attr.priority;
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+ __entry->shadow_ctx = is_shadow_context(req->gem_context);
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+ __entry->hw_id = req->gem_context->hw_id;
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+ __entry->vgt_id = get_vgt_id(req->gem_context);
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+ __entry->pid = is_shadow_context(req->gem_context) ?
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+ get_pid_shadowed(req->gem_context, req->engine) :
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+ pid_nr(req->gem_context->pid);
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+ ),
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+
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+ TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u, "
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+ "priority=%d (%d), is_shadow_ctx=%u, hw_id=%u, "
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+ "vgt_id=%u, pid=%u", __entry->dev, __entry->ring,
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+ __entry->ctx, __entry->seqno, __entry->global,
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+ __entry->prio_req, __entry->prio_ctx, __entry->shadow_ctx,
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+ __entry->hw_id, __entry->vgt_id, __entry->pid)
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+);
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+
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+DEFINE_EVENT(i915_multi_domains, i915_request_add_domain,
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+ TP_PROTO(struct i915_request *req),
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+ TP_ARGS(req)
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+);
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+
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#if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
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DEFINE_EVENT(i915_request, i915_request_submit,
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TP_PROTO(struct i915_request *rq),
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diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
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index e389909..8552e73 100644
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--- a/drivers/gpu/drm/i915/intel_drv.h
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+++ b/drivers/gpu/drm/i915/intel_drv.h
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@@ -1394,6 +1394,11 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
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return dev_priv->runtime_pm.irqs_enabled;
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}
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+bool is_shadow_context(struct i915_gem_context *ctx);
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+int get_vgt_id(struct i915_gem_context *ctx);
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+int get_pid_shadowed(struct i915_gem_context *ctx,
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+ struct intel_engine_cs *engine);
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+
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int intel_get_crtc_scanline(struct intel_crtc *crtc);
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void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
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u8 pipe_mask);
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--
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https://clearlinux.org
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