167 lines
6.2 KiB
Diff
167 lines
6.2 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Liu Xinyun <xinyun.liu@intel.com>
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Date: Wed, 20 Mar 2019 13:37:12 +0800
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Subject: [PATCH] drm/i915/gvt: enable cursor plane emulation
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Add handler to intercept cursor plane operation and update h/w with value
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from guest OS.
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The watermark from the guest OS and the predefined ddb in the service OS
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are set to hardware together. It's workable but has risk. The guest OS
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driver has a set of ddb and watermark setting. The ddb topology might be
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conflict with the predefined ddb in virtualization case. So it is better
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to re-compute the watermark in service OS with the plane information
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from guest OS and predefined ddb together in future.
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v3: combine small patches to enable cursor plane
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v2: remove magic number and add comment
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Tracked-On: projectacrn/acrn-hypervisor#3106
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Signed-off-by: Liu Xinyun <xinyun.liu@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/gvt/handlers.c | 104 ++++++++++++++++++++++------
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1 file changed, 83 insertions(+), 21 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index 5eeb655edfaf..63c830d57fad 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -2054,25 +2054,25 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
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MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
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- MMIO_D(CURCNTR(PIPE_A), D_ALL);
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- MMIO_D(CURCNTR(PIPE_B), D_ALL);
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- MMIO_D(CURCNTR(PIPE_C), D_ALL);
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+ MMIO_D(CURCNTR(PIPE_A), D_BDW);
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+ MMIO_D(CURCNTR(PIPE_B), D_BDW);
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+ MMIO_D(CURCNTR(PIPE_C), D_BDW);
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- MMIO_D(CURPOS(PIPE_A), D_ALL);
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- MMIO_D(CURPOS(PIPE_B), D_ALL);
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- MMIO_D(CURPOS(PIPE_C), D_ALL);
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+ MMIO_D(CURPOS(PIPE_A), D_BDW);
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+ MMIO_D(CURPOS(PIPE_B), D_BDW);
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+ MMIO_D(CURPOS(PIPE_C), D_BDW);
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- MMIO_D(CURBASE(PIPE_A), D_ALL);
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- MMIO_D(CURBASE(PIPE_B), D_ALL);
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- MMIO_D(CURBASE(PIPE_C), D_ALL);
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+ MMIO_D(CURBASE(PIPE_A), D_BDW);
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+ MMIO_D(CURBASE(PIPE_B), D_BDW);
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+ MMIO_D(CURBASE(PIPE_C), D_BDW);
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- MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
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- MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
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- MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
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+ MMIO_D(CUR_FBC_CTL(PIPE_A), D_BDW);
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+ MMIO_D(CUR_FBC_CTL(PIPE_B), D_BDW);
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+ MMIO_D(CUR_FBC_CTL(PIPE_C), D_BDW);
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- MMIO_D(_MMIO(0x700ac), D_ALL);
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- MMIO_D(_MMIO(0x710ac), D_ALL);
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- MMIO_D(_MMIO(0x720ac), D_ALL);
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+ MMIO_D(CURSURFLIVE(PIPE_A), D_BDW);
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+ MMIO_D(CURSURFLIVE(PIPE_B), D_BDW);
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+ MMIO_D(CURSURFLIVE(PIPE_C), D_BDW);
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MMIO_D(_MMIO(0x70090), D_ALL);
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MMIO_D(_MMIO(0x70094), D_ALL);
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@@ -2987,6 +2987,43 @@ static int pv_plane_wm_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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return 0;
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}
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+static int skl_cursor_surf_write(struct intel_vgpu *vgpu, unsigned int offset,
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+ void *p_data, unsigned int bytes)
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+{
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+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+ unsigned int pipe = SKL_PLANE_REG_TO_PIPE(offset);
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+
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+ write_vreg(vgpu, offset, p_data, bytes);
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+ vgpu_vreg_t(vgpu, CURSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
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+
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+ if ((vgpu_vreg_t(vgpu, PIPECONF(pipe)) & I965_PIPECONF_ACTIVE) &&
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+ (vgpu->gvt->pipe_info[pipe].plane_owner[0] == vgpu->id)) {
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+ /* Each pipe has a primary and a cursor plane. Here we use
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+ * primary plane's ownership to decide whether the vm has the
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+ * cursor.
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+ */
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+ I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
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+ }
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+
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+ return 0;
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+}
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+
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+
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+static int skl_cursor_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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+ void *p_data, unsigned int bytes)
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+{
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+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+ unsigned int pipe = SKL_PLANE_REG_TO_PIPE(offset);
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+
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+ write_vreg(vgpu, offset, p_data, bytes);
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+ if ((vgpu_vreg_t(vgpu, PIPECONF(pipe)) & I965_PIPECONF_ACTIVE) &&
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+ (vgpu->gvt->pipe_info[pipe].plane_owner[0] == vgpu->id)) {
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+ I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
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+ }
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+
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+ return 0;
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+}
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+
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#define MMIO_PIPES_SDH(prefix, plane, s, d, r, w) do { \
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int pipe; \
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for_each_pipe(dev_priv, pipe) \
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@@ -3137,17 +3174,42 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
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pv_plane_wm_mmio_write);
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MMIO_PLANES_DH(PLANE_BUF_CFG, D_SKL_PLUS, NULL, NULL);
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+
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+ MMIO_DH(CURCNTR(PIPE_A), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CURCNTR(PIPE_B), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CURCNTR(PIPE_C), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+
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+ MMIO_DH(CURPOS(PIPE_A), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CURPOS(PIPE_B), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CURPOS(PIPE_C), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+
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+ MMIO_DH(CURBASE(PIPE_A), D_SKL_PLUS, NULL, skl_cursor_surf_write);
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+ MMIO_DH(CURBASE(PIPE_B), D_SKL_PLUS, NULL, skl_cursor_surf_write);
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+ MMIO_DH(CURBASE(PIPE_C), D_SKL_PLUS, NULL, skl_cursor_surf_write);
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+
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+ MMIO_DH(CUR_FBC_CTL(PIPE_A), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CUR_FBC_CTL(PIPE_B), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CUR_FBC_CTL(PIPE_C), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+
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+ MMIO_DH(CURSURFLIVE(PIPE_A), D_SKL_PLUS, NULL, NULL);
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+ MMIO_DH(CURSURFLIVE(PIPE_B), D_SKL_PLUS, NULL, NULL);
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+ MMIO_DH(CURSURFLIVE(PIPE_C), D_SKL_PLUS, NULL, NULL);
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+
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+
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MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
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MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
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MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
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- MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
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- MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
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- MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
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+ MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS,
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+ NULL, skl_cursor_mmio_write);
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+ MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS,
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+ NULL, skl_cursor_mmio_write);
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+ MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS,
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+ NULL, skl_cursor_mmio_write);
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- MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
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- MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
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- MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
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+ MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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+ MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, skl_cursor_mmio_write);
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MMIO_D(_MMIO(0x8f074), D_SKL_PLUS);
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MMIO_D(_MMIO(0x8f004), D_SKL_PLUS);
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--
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https://clearlinux.org
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