37 lines
1.6 KiB
Diff
37 lines
1.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: qianmenx <qianx.meng@intel.com>
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Date: Tue, 21 May 2019 11:37:37 +0800
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Subject: [PATCH] media: intel-ipu4: ox03a10: change metadata set
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change digital gain reg number to 3 of metadata
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Change-Id: Ifdd173db9a7f40088436a8a5acb2431363a2a508
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Tracked-On: PKT-2588
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Tracked-On: #JIIAP-801
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Signed-off-by: qianmenx <qianx.meng@intel.com>
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Signed-off-by: Meng Wei <wei.meng@intel.com>
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---
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drivers/media/i2c/crlmodule/crl_ox03a10_common.h | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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index 636ac23da3a3..484e89526226 100644
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--- a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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@@ -532,9 +532,9 @@ static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
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{ 0x483e, CRL_REG_LEN_08BIT, 0x02 },/* frame counter */
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{ 0x3501, CRL_REG_LEN_08BIT, 0x02 },/* DCG exp */
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{ 0x3581, CRL_REG_LEN_08BIT, 0x02 },/* VS exp */
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- { 0x350a, CRL_REG_LEN_08BIT, 0x02 },/* HCG Dgain */
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- { 0x354a, CRL_REG_LEN_08BIT, 0x02 },/* LCG Dgain */
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- { 0x358a, CRL_REG_LEN_08BIT, 0x02 },/* VS Dgain */
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+ { 0x350a, CRL_REG_LEN_08BIT, 0x03 },/* HCG Dgain */
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+ { 0x354a, CRL_REG_LEN_08BIT, 0x03 },/* LCG Dgain */
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+ { 0x358a, CRL_REG_LEN_08BIT, 0x03 },/* VS Dgain */
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{ 0x3508, CRL_REG_LEN_08BIT, 0x02 },/* HCG Again */
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{ 0x3548, CRL_REG_LEN_08BIT, 0x02 },/* LCG Again */
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{ 0x3588, CRL_REG_LEN_08BIT, 0x02 },/* VS Again */
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--
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https://clearlinux.org
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