76 lines
2.3 KiB
Diff
76 lines
2.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Min He <min.he@intel.com>
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Date: Wed, 10 Jul 2019 06:59:18 +0000
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Subject: [PATCH] drm/i915: add GEN9 cache sharing control in debugfs
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To support cache sharing QoS, we added support for Gen9 in this patch.
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Tracked-On: PKT-2559
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Tracked-On: projectacrn/acrn-hypervisor#3392
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Signed-off-by: Min He <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/i915_debugfs.c | 16 +++++++++++++---
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drivers/gpu/drm/i915/i915_reg.h | 3 +++
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2 files changed, 16 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
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index 320564fd8b4b..61b8a1ff7adc 100644
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--- a/drivers/gpu/drm/i915/i915_debugfs.c
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+++ b/drivers/gpu/drm/i915/i915_debugfs.c
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@@ -4267,7 +4267,8 @@ i915_cache_sharing_get(void *data, u64 *val)
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struct drm_i915_private *dev_priv = data;
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u32 snpcr;
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- if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
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+ if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)
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+ || IS_GEN9(dev_priv)))
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return -ENODEV;
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intel_runtime_pm_get(dev_priv);
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@@ -4285,9 +4286,10 @@ static int
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i915_cache_sharing_set(void *data, u64 val)
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{
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struct drm_i915_private *dev_priv = data;
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- u32 snpcr;
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+ u32 snpcr, idicr;
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- if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
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+ if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)
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+ || IS_GEN9(dev_priv)))
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return -ENODEV;
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if (val > 3)
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@@ -4302,6 +4304,14 @@ i915_cache_sharing_set(void *data, u64 val)
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snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
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I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
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+
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+ if (IS_GEN9(dev_priv)) {
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+ idicr = I915_READ(HSW_IDICR);
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+ idicr &= ~IDI_QOS_MASK;
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+ idicr |= (val << IDI_QOS_SHIFT);
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+ I915_WRITE(HSW_IDICR, idicr);
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+ }
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+
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intel_runtime_pm_put(dev_priv);
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return 0;
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}
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index 673998b338ed..12d3d15b45fe 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -8377,6 +8377,9 @@ enum {
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#define HSW_IDICR _MMIO(0x9008)
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#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
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+#define IDI_QOS_MASK (3 << 22)
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+#define IDI_QOS_SHIFT 22
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+
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#define HSW_EDRAM_CAP _MMIO(0x120010)
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#define EDRAM_ENABLED 0x1
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#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
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--
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https://clearlinux.org
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