46 lines
1.7 KiB
Diff
46 lines
1.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Zhipeng Gong <zhipeng.gong@intel.com>
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Date: Mon, 12 Nov 2018 09:50:48 +0800
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Subject: [PATCH] drm/i915/gvt: fix gvtbuffer ioctl tile format issue
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primary buffer decoder function return tile format with 10 bits shift.
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while gvtbuffer ioctl args tiled is defined to one byte, as a result
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zero is alwasy returned to user space.
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This is used to convert the driver tile format to align the requirement
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of gvtbuffer_ioctl args.
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Tracked-On: PKT-1592
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Tracked-On: projectacrn/acrn-hypervisor#1576
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Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/i915_gem_gvtbuffer.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c b/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c
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index fb1ced042a4e..c34599674867 100644
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--- a/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c
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+++ b/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c
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@@ -65,6 +65,8 @@ static const struct drm_i915_gem_object_ops i915_gem_gvtbuffer_ops = {
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#define GEN7_DECODE_PTE(pte) \
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((dma_addr_t)(((((u64)pte) & 0x7f0) << 28) | (u64)(pte & 0xfffff000)))
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+#define PLANE_CTL_TILED_SHIFT 10
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+
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static struct sg_table *
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i915_create_sg_pages_for_gvtbuffer(struct drm_device *dev,
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u32 start, u32 num_pages)
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@@ -185,7 +187,7 @@ static int gvt_decode_information(struct drm_device *dev,
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args->bpp = p.bpp;
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args->hw_format = p.hw_format;
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args->drm_format = p.drm_format;
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- args->tiled = p.tiled;
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+ args->tiled = p.tiled >> PLANE_CTL_TILED_SHIFT;
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} else if ((args->plane_id) == I915_GVT_PLANE_CURSOR) {
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ret = intel_vgpu_decode_cursor_plane(vgpu, &c);
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if (ret)
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--
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https://clearlinux.org
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