179 lines
5.6 KiB
Diff
179 lines
5.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Satyeshwar Singh <satyeshwar.singh@intel.com>
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Date: Fri, 5 Oct 2018 13:52:11 -0700
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Subject: [PATCH] drm/i915: Optimize watermark calculation for plane
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restrictions
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The same code was being used in skl_build_plane_wm and
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skl_build_pipe_all_plane_wm which was redundant. Stripped out this
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code into a common function.
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Signed-off-by: Satyeshwar Singh <satyeshwar.singh@intel.com>
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---
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drivers/gpu/drm/i915/intel_pm.c | 106 +++++++++++++++++---------------
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1 file changed, 55 insertions(+), 51 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 4e3af2424028..968ac86159f2 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -4944,13 +4944,63 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
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trans_wm->plane_en = false;
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}
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+static int skl_build_plane_wm(struct intel_crtc_state *cstate,
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+ struct skl_ddb_allocation *ddb,
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+ struct skl_pipe_wm *pipe_wm,
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+ int pipe,
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+ enum plane_id plane_id,
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+ struct intel_plane_state *intel_pstate)
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+{
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+ struct drm_device *dev = cstate->base.crtc->dev;
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+ const struct drm_i915_private *dev_priv = to_i915(dev);
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+ struct skl_plane_wm *wm;
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+ struct skl_wm_params wm_params;
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+ uint16_t ddb_blocks;
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+ int ret;
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+
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+ wm = &pipe_wm->planes[plane_id];
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+ ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
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+
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+ ret = skl_compute_plane_wm_params(dev_priv, cstate,
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+ intel_pstate, &wm_params, 0);
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+ if (ret)
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+ return ret;
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+
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+ ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
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+ intel_pstate, &wm_params, wm, 0, plane_id);
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+ if (ret)
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+ return ret;
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+
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+ skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
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+ ddb_blocks, &wm->trans_wm);
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+
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+ /* uv plane watermarks must also be validated for NV12/Planar */
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+ if (wm_params.is_planar) {
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+ memset(&wm_params, 0, sizeof(struct skl_wm_params));
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+ wm->is_planar = true;
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+
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+ ret = skl_compute_plane_wm_params(dev_priv, cstate,
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+ intel_pstate,
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+ &wm_params, 1);
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+ if (ret)
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+ return ret;
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+
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+ ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
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+ intel_pstate, &wm_params,
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+ wm, 1, plane_id);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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static int skl_build_pipe_all_plane_wm(struct intel_crtc_state *cstate,
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struct skl_ddb_allocation *ddb,
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struct skl_pipe_wm *pipe_wm)
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{
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struct drm_device *dev = cstate->base.crtc->dev;
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const struct drm_i915_private *dev_priv = to_i915(dev);
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- struct skl_plane_wm *wm;
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struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
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struct drm_crtc_state *crtc_state = &cstate->base;
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struct drm_plane *plane;
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@@ -4971,8 +5021,6 @@ static int skl_build_pipe_all_plane_wm(struct intel_crtc_state *cstate,
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* also assume cpp = 4 and tiling = x_tiled.
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*/
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for_each_universal_plane(dev_priv, pipe, plane_id) {
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- struct skl_wm_params wm_params;
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- uint16_t ddb_blocks;
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intel_pstate = NULL;
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drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
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@@ -4982,20 +5030,10 @@ static int skl_build_pipe_all_plane_wm(struct intel_crtc_state *cstate,
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}
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}
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- wm = &pipe_wm->planes[plane_id];
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- ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
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- ret = skl_compute_plane_wm_params(dev_priv, cstate,
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- intel_pstate, &wm_params, 0);
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- if (ret)
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- return ret;
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-
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- ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
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- intel_pstate, &wm_params, wm, 0, plane_id);
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+ ret = skl_build_plane_wm(cstate, ddb, pipe_wm,
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+ pipe, plane_id, (struct intel_plane_state *) intel_pstate);
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if (ret)
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return ret;
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-
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- skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
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- ddb_blocks, &wm->trans_wm);
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}
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pipe_wm->linetime = skl_compute_linetime_wm(cstate);
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@@ -5006,12 +5044,9 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
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struct skl_ddb_allocation *ddb,
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struct skl_pipe_wm *pipe_wm)
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{
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- struct drm_device *dev = cstate->base.crtc->dev;
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struct drm_crtc_state *crtc_state = &cstate->base;
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- const struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_plane *plane;
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const struct drm_plane_state *pstate;
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- struct skl_plane_wm *wm;
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int ret;
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/*
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@@ -5024,43 +5059,12 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
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const struct intel_plane_state *intel_pstate =
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to_intel_plane_state(pstate);
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enum plane_id plane_id = to_intel_plane(plane)->id;
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- struct skl_wm_params wm_params;
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enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
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- uint16_t ddb_blocks;
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- wm = &pipe_wm->planes[plane_id];
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- ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
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-
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- ret = skl_compute_plane_wm_params(dev_priv, cstate,
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- intel_pstate, &wm_params, 0);
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+ ret = skl_build_plane_wm(cstate, ddb, pipe_wm,
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+ pipe, plane_id, (struct intel_plane_state *) intel_pstate);
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if (ret)
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return ret;
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-
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- ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
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- intel_pstate, &wm_params, wm, 0, plane_id);
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- if (ret)
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- return ret;
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-
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- skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
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- ddb_blocks, &wm->trans_wm);
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-
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- /* uv plane watermarks must also be validated for NV12/Planar */
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- if (wm_params.is_planar) {
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- memset(&wm_params, 0, sizeof(struct skl_wm_params));
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- wm->is_planar = true;
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-
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- ret = skl_compute_plane_wm_params(dev_priv, cstate,
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- intel_pstate,
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- &wm_params, 1);
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- if (ret)
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- return ret;
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-
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- ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
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- intel_pstate, &wm_params,
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- wm, 1, plane_id);
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- if (ret)
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- return ret;
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- }
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}
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pipe_wm->linetime = skl_compute_linetime_wm(cstate);
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--
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https://clearlinux.org
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