164 lines
5.2 KiB
Diff
164 lines
5.2 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Fei Jiang <fei.jiang@intel.com>
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Date: Wed, 29 Aug 2018 11:49:44 +0800
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Subject: [PATCH] drm/i915/gvt: pvmmio optimization for plane wm register
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update
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It is performance optimization to reduce plane wm related register trap
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counter. When update plane wm, multiple plane wm related registers are
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updated together, optimize it to firstly cache all register values in
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share page, then only PLANE_NV12_BUF_CFG register writing is trapped.
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Plane pvmmio level is PVMMIO_PLANE_WM_UPDATE.
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If plane restriction feature is enabled, trap handlers for plane wm
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related register are null, then directly return.
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Patch for both SOS and UOS.
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V2: when plane restriction feature is enabled, SOS trap handlers for
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plane wm related registers are null, then don't trap
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Signed-off-by: Fei Jiang <fei.jiang@intel.com>
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Reviewed-by: Min He <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/i915_pvinfo.h | 11 ++++-
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drivers/gpu/drm/i915/intel_pm.c | 79 ++++++++++++++++++++++++++++++
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2 files changed, 89 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
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index 9c76cab07010..82ab32e87805 100644
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--- a/drivers/gpu/drm/i915/i915_pvinfo.h
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+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
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@@ -75,6 +75,13 @@ struct pv_plane_update {
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u32 plane_ctl;
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};
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+struct pv_plane_wm_update {
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+ u32 max_wm_level;
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+ u32 plane_wm_level[8];
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+ u32 plane_trans_wm_level;
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+ u32 plane_buf_cfg;
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+};
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+
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struct pv_ppgtt_update {
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u64 pdp;
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u64 start;
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@@ -89,8 +96,9 @@ struct gvt_shared_page {
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u32 elsp_data[4];
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u32 reg_addr;
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struct pv_plane_update pv_plane;
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+ struct pv_plane_wm_update pv_plane_wm;
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struct pv_ppgtt_update pv_ppgtt;
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- u32 rsvd2[0x400 - 30];
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+ u32 rsvd2[0x400 - 40];
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};
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#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
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@@ -101,6 +109,7 @@ struct gvt_shared_page {
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enum pvmmio_levels {
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PVMMIO_ELSP_SUBMIT = 0x1,
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PVMMIO_PLANE_UPDATE = 0x2,
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+ PVMMIO_PLANE_WM_UPDATE = 0x4,
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PVMMIO_PPGTT_UPDATE = 0x10,
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};
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 0fc9fdc4b4a0..bf08b3bc6741 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -5008,6 +5008,70 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
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I915_WRITE(reg, val);
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}
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+static void skl_pv_write_wm_level(u32 *plane_wm_level,
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+ const struct skl_wm_level *level)
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+{
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+ uint32_t val = 0;
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+
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+ if (level->plane_en) {
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+ val |= PLANE_WM_EN;
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+ val |= level->plane_res_b;
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+ val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
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+ }
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+
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+ *plane_wm_level = val;
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+}
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+
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+static void skl_pv_ddb_entry_write(u32 *plane_cfg,
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+ const struct skl_ddb_entry *entry)
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+{
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+ if (entry->end)
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+ *plane_cfg = (entry->end - 1) << 16 | entry->start;
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+ else
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+ *plane_cfg = 0;
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+}
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+
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+static void skl_pv_write_plane_wm(struct intel_crtc *intel_crtc,
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+ const struct skl_plane_wm *wm,
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+ const struct skl_ddb_allocation *ddb,
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+ enum plane_id plane_id)
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+{
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+ int i, level;
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+ struct pv_plane_wm_update tmp_plane_wm;
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+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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+ int max_level = ilk_wm_max_level(dev_priv);
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+ u32 __iomem *pv_plane_wm = (u32 *)&(dev_priv->shared_page->pv_plane_wm);
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+ enum pipe pipe = intel_crtc->pipe;
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+
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+ memset(&tmp_plane_wm, 0, sizeof(struct pv_plane_wm_update));
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+ tmp_plane_wm.max_wm_level = max_level;
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+ for (level = 0; level <= max_level; level++) {
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+ skl_pv_write_wm_level(&tmp_plane_wm.plane_wm_level[level],
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+ &wm->wm[level]);
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+ }
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+ skl_pv_write_wm_level(&tmp_plane_wm.plane_trans_wm_level,
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+ &wm->trans_wm);
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+
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+ if (wm->is_planar) {
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+ skl_pv_ddb_entry_write(&tmp_plane_wm.plane_buf_cfg,
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+ &ddb->uv_plane[pipe][plane_id]);
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+ } else {
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+ skl_pv_ddb_entry_write(&tmp_plane_wm.plane_buf_cfg,
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+ &ddb->plane[pipe][plane_id]);
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+ }
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+
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+ spin_lock(&dev_priv->shared_page_lock);
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+ for (i = 0; i < sizeof(struct pv_plane_wm_update) / 4; i++)
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+ writel(*((u32 *)(&tmp_plane_wm) + i), pv_plane_wm + i);
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+ if (wm->is_planar)
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+ skl_ddb_entry_write(dev_priv,
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+ PLANE_NV12_BUF_CFG(pipe, plane_id),
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+ &ddb->plane[pipe][plane_id]);
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+ else
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+ I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
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+ spin_unlock(&dev_priv->shared_page_lock);
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+}
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+
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static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
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const struct skl_plane_wm *wm,
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const struct skl_ddb_allocation *ddb,
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@@ -5019,6 +5083,21 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
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int level, max_level = ilk_wm_max_level(dev_priv);
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enum pipe pipe = intel_crtc->pipe;
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+ if (INTEL_GEN(dev_priv) < 11) {
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+ /*
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+ * when plane restriction feature is enabled,
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+ * sos trap handlers for plane wm related registers are null
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+ */
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+ /* TODO: uncomment when plane restriction feature is enabled */
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+#if 0
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+ if (i915_modparams.avail_planes_per_pipe)
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+ return;
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+#endif
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+ if (PVMMIO_LEVEL(dev_priv, PVMMIO_PLANE_WM_UPDATE))
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+ return skl_pv_write_plane_wm(intel_crtc, wm,
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+ ddb, plane_id);
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+ }
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+
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for (level = 0; level <= max_level; level++) {
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skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
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&wm->wm[level]);
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--
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https://clearlinux.org
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