202 lines
7.9 KiB
Diff
202 lines
7.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Min He <min.he@intel.com>
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Date: Thu, 4 Jan 2018 21:48:47 +0800
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Subject: [PATCH] drm/i915/gvt: show pid/hw_id of current DomU process in
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debugfs
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v1: show pid and hw id of current DomU process when showing shadow context
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status
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This allows us to identify which process a domu workload has come from.
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v2: expose HW context id to debugfs
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This patch expose the HW context id to the debugfs node, so that vtune
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can utilize this context id to match with the one exposed by MD API.
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v3: When storing DomU pid and hw id in the HWS page, offset them by the
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vgpu id.
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When there were multiple DomUs running, they would all write their pid
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to the same address in the HWS page. When we checked i915_context_status
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each shadow context would show the same current pid and hw id. By
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offsetting the writes by the DomU's ID, we can see the details for each
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shadow context correctly. This fixes defect 201282.
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Change-Id: I106fae75af5963f043286acd604d3bab02b87c17
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Signed-off-by: Min He <min.he@intel.com>
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Signed-off-by: Daniel van der Wath <danielx.j.van.der.wath@intel.com>
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Signed-off-by: Fei Jiang <fei.jiang@intel.com>
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Reviewed-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-by: Abes, Brahim <brahimx.abes@intel.com>
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-on:
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/gvt/scheduler.c | 38 +++++++++++++++++++++++++
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drivers/gpu/drm/i915/i915_debugfs.c | 26 ++++++++++++++++-
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drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++
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drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++++
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4 files changed, 76 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
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index 1d25ee3c1277..c28bc9a2fffa 100644
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--- a/drivers/gpu/drm/i915/gvt/scheduler.c
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+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
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@@ -435,6 +435,38 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
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return ret;
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}
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+static void gen8_shadow_pid_cid(struct intel_vgpu_workload *workload)
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+{
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+ int ring_id = workload->ring_id;
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+ struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
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+ struct intel_engine_cs *engine = dev_priv->engine[ring_id];
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+ u32 *cs;
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+
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+ /* Copy the PID and CID from the guest's HWS page to the host's one */
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+ cs = intel_ring_begin(workload->req, 16);
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+ *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
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+ *cs++ = i915_mmio_reg_offset(NOPID);
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+ *cs++ = (workload->ctx_desc.lrca << I915_GTT_PAGE_SHIFT) +
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+ I915_GEM_HWS_PID_ADDR;
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+ *cs++ = 0;
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+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
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+ *cs++ = i915_mmio_reg_offset(NOPID);
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+ *cs++ = engine->status_page.ggtt_offset + I915_GEM_HWS_PID_ADDR +
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+ (workload->vgpu->id << MI_STORE_DWORD_INDEX_SHIFT);
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+ *cs++ = 0;
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+ *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
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+ *cs++ = i915_mmio_reg_offset(NOPID);
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+ *cs++ = (workload->ctx_desc.lrca << I915_GTT_PAGE_SHIFT) +
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+ I915_GEM_HWS_CID_ADDR;
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+ *cs++ = 0;
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+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
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+ *cs++ = i915_mmio_reg_offset(NOPID);
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+ *cs++ = engine->status_page.ggtt_offset + I915_GEM_HWS_CID_ADDR +
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+ (workload->vgpu->id << MI_STORE_DWORD_INDEX_SHIFT);
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+ *cs++ = 0;
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+ intel_ring_advance(workload->req, cs);
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+}
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+
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static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
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static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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@@ -633,6 +665,8 @@ static int prepare_workload(struct intel_vgpu_workload *workload)
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goto err_unpin_mm;
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}
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+ gen8_shadow_pid_cid(workload);
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+
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ret = prepare_shadow_batch_buffer(workload);
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if (ret) {
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gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
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@@ -1180,6 +1214,10 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
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if (IS_ERR(s->shadow_ctx))
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return PTR_ERR(s->shadow_ctx);
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+ if (!s->shadow_ctx->name) {
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+ s->shadow_ctx->name = kasprintf(GFP_KERNEL, "Shadow Context %d", vgpu->id);
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+ }
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+
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bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
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s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
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diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
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index b2e0c2348882..4a1330a42a28 100644
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--- a/drivers/gpu/drm/i915/i915_debugfs.c
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+++ b/drivers/gpu/drm/i915/i915_debugfs.c
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@@ -1943,6 +1943,19 @@ static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
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ring->space, ring->head, ring->tail, ring->emit);
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}
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+static void describe_ctx_ring_shadowed(struct seq_file *m,
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+ struct i915_gem_context *ctx, struct intel_ring *ring,
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+ struct intel_engine_cs *engine)
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+{
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+ int pid, cid, vgt_id;
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+
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+ sscanf(ctx->name, "Shadow Context %d", &vgt_id);
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+ pid = intel_read_status_page(engine, I915_GEM_HWS_PID_INDEX + vgt_id);
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+ cid = intel_read_status_page(engine, I915_GEM_HWS_CID_INDEX + vgt_id);
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+ seq_printf(m, " (Current DomU Process PID: %d, CID: %d)",
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+ pid, cid);
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+}
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+
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static int i915_context_status(struct seq_file *m, void *unused)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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@@ -1957,6 +1970,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
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return ret;
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list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
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+ bool is_shadow_context = false;
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seq_printf(m, "HW context %u ", ctx->hw_id);
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if (ctx->pid) {
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struct task_struct *task;
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@@ -1967,6 +1981,9 @@ static int i915_context_status(struct seq_file *m, void *unused)
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task->comm, task->pid);
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put_task_struct(task);
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}
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+ } else if (ctx->name && !strncmp(ctx->name, "Shadow Context", 14)) {
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+ seq_puts(m, "DomU Shadow Context ");
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+ is_shadow_context = true;
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} else if (IS_ERR(ctx->file_priv)) {
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seq_puts(m, "(deleted) ");
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} else {
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@@ -1979,12 +1996,19 @@ static int i915_context_status(struct seq_file *m, void *unused)
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for_each_engine(engine, dev_priv, id) {
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struct intel_context *ce =
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to_intel_context(ctx, engine);
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+ u64 lrc_desc = ce->lrc_desc;
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+ seq_printf(m, "ctx id 0x%x ", (uint32_t)((lrc_desc >> 12) &
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+ 0xFFFFF));
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seq_printf(m, "%s: ", engine->name);
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if (ce->state)
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describe_obj(m, ce->state->obj);
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- if (ce->ring)
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+ if (ce->ring) {
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describe_ctx_ring(m, ce->ring);
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+ if(is_shadow_context)
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+ describe_ctx_ring_shadowed(m, ctx,
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+ ce->ring, engine);
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+ }
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seq_putc(m, '\n');
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}
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diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
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index c8d5324f2d38..adfe6901b8d5 100644
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--- a/drivers/gpu/drm/i915/intel_lrc.c
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+++ b/drivers/gpu/drm/i915/intel_lrc.c
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@@ -2750,6 +2750,14 @@ populate_lr_context(struct i915_gem_context *ctx,
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
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CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
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+ /* write the context's pid and hw_id/cid to the per-context HWS page */
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+ if(intel_vgpu_active(engine->i915) && pid_nr(ctx->pid)) {
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+ *(u32*)(vaddr + LRC_PPHWSP_PN * PAGE_SIZE + I915_GEM_HWS_PID_ADDR)
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+ = pid_nr(ctx->pid) & 0x3fffff;
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+ *(u32*)(vaddr + LRC_PPHWSP_PN * PAGE_SIZE + I915_GEM_HWS_CID_ADDR)
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+ = ctx->hw_id & 0x3fffff;
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+ }
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+
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err_unpin_ctx:
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i915_gem_object_unpin_map(ctx_obj);
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return ret;
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diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
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index 4f39f6b5d1e0..83833ce2a4f0 100644
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--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
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+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
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@@ -797,6 +797,11 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
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#define I915_GEM_HWS_SCRATCH_INDEX 0x40
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#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
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+#define I915_GEM_HWS_PID_INDEX 0x50
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+#define I915_GEM_HWS_PID_ADDR (I915_GEM_HWS_PID_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
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+#define I915_GEM_HWS_CID_INDEX 0x58
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+#define I915_GEM_HWS_CID_ADDR (I915_GEM_HWS_CID_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
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+
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#define I915_HWS_CSB_BUF0_INDEX 0x10
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#define I915_HWS_CSB_WRITE_INDEX 0x1f
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#define CNL_HWS_CSB_WRITE_INDEX 0x2f
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--
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https://clearlinux.org
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