206 lines
6.3 KiB
Diff
206 lines
6.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Sanyog Kale <sanyog.r.kale@intel.com>
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Date: Sun, 20 Nov 2016 20:16:25 +0530
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Subject: [PATCH] SoundWire: Hardcoding in bus driver for SVFPGA PDM codec.
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SVFPGA PDM codec implements the codec in orthogonal way to
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MIPI to verify the PDM on CNL Master controller. Added hardcodings
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to support SVFPGA. This is just for testing. This patch wont
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be upstreamed.
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Change-Id: I42b0fd5a16e59577a89bbab7bc024aed1b04c222
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Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
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Reviewed-on:
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Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com>
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---
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drivers/sdw/sdw_bwcalc.c | 83 ++++++++++++++++++++++++++++++++--------
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1 file changed, 68 insertions(+), 15 deletions(-)
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diff --git a/drivers/sdw/sdw_bwcalc.c b/drivers/sdw/sdw_bwcalc.c
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index 9c1ebc3297d2..b76ace3b0de7 100644
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--- a/drivers/sdw/sdw_bwcalc.c
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+++ b/drivers/sdw/sdw_bwcalc.c
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@@ -27,8 +27,19 @@
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#define MAXCLOCKFREQ 6
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-#define MAXCLOCKFREQ 6
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+/* For PDM Capture, frameshape used is 50x10 */
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+int rows[MAX_NUM_ROWS] = {50, 100, 48, 60, 64, 72, 75, 80, 90,
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+ 96, 125, 144, 147, 120, 128, 150,
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+ 160, 180, 192, 200, 240, 250, 256};
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+
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+int cols[MAX_NUM_COLS] = {10, 2, 4, 6, 8, 12, 14, 16};
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+int clock_freq[MAXCLOCKFREQ] = {19200000, 19200000,
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+ 19200000, 19200000,
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+ 19200000, 19200000};
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+
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+#else
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/* TBD: Currently we are using 100x2 as frame shape. to be removed later */
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int rows[MAX_NUM_ROWS] = {100, 48, 50, 60, 64, 72, 75, 80, 90,
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96, 125, 144, 147, 120, 128, 150,
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@@ -44,7 +55,7 @@ int cols[MAX_NUM_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
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int clock_freq[MAXCLOCKFREQ] = {9600000, 9600000,
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9600000, 9600000,
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9600000, 9600000};
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-
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+#endif
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struct sdw_num_to_col sdw_num_col_mapping[MAX_NUM_COLS] = {
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{0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, {5, 12}, {6, 14}, {7, 16},
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@@ -104,20 +115,27 @@ int sdw_mstr_bw_init(struct sdw_bus *sdw_bs)
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sdw_bs->bandwidth = 0;
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sdw_bs->system_interval = 0;
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sdw_bs->frame_freq = 0;
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- /* TBD: Base Clock frequency should be read from
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- * master capabilities
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- * Currenly hardcoding to 9.6MHz
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- */
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- sdw_bs->clk_freq = 9.6*1000*1000;
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sdw_bs->clk_state = SDW_CLK_STATE_ON;
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/* TBD: to be removed later */
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/* Assumption is these should be already filled */
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sdw_mstr_cap = &sdw_bs->mstr->mstr_capabilities;
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- sdw_mstr_cap->base_clk_freq = 9.6 * 1000 * 1000;
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sdw_mstr_cap->monitor_handover_supported = false;
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sdw_mstr_cap->highphy_capable = false;
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+ /* TBD: For PDM capture to be removed later */
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+ sdw_bs->clk_freq = 9.6 * 1000 * 1000 * 2;
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+ sdw_mstr_cap->base_clk_freq = 9.6 * 1000 * 1000 * 2;
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+#else
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+ /* TBD: Base Clock frequency should be read from
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+ * master capabilities
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+ * Currenly hardcoding to 9.6MHz
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+ */
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+ sdw_bs->clk_freq = 9.6 * 1000 * 1000;
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+ sdw_mstr_cap->base_clk_freq = 9.6 * 1000 * 1000;
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+
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+#endif
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdw_mstr_bw_init);
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@@ -201,8 +219,24 @@ int sdw_cfg_slv_params(struct sdw_bus *mstr_bs,
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u8 wbuf[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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u8 wbuf1[2] = {0, 0};
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u8 rbuf[1] = {0};
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- u8 rbuf1[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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- u8 rbuf2[2] = {0, 0};
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+
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+
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+ /*
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+ * The below hardcoding is required
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+ * for running PDM capture with SV conora card
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+ * because the transport params of card is not
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+ * same as master parameters. Also not all
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+ * standard registers are valid.
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+ */
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+ t_slv_params->blockgroupcontrol_valid = false;
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+ t_slv_params->sample_interval = 50;
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+ t_slv_params->offset1 = 0;
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+ t_slv_params->offset2 = 0;
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+ t_slv_params->hstart = 1;
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+ t_slv_params->hstop = 6;
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+ p_slv_params->word_length = 30;
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+#endif
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/* Program slave alternate bank with all transport parameters */
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/* DPN_BlockCtrl2 */
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@@ -259,7 +293,11 @@ int sdw_cfg_slv_params(struct sdw_bus *mstr_bs,
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wr_msg.ssp_tag = 0x0;
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wr_msg.flag = SDW_MSG_FLAG_WRITE;
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+ wr_msg.len = (5 + (1 * (t_slv_params->blockgroupcontrol_valid)));
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+#else
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wr_msg.len = (7 + (1 * (t_slv_params->blockgroupcontrol_valid)));
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+#endif
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wr_msg.slave_addr = slv_rt->slave->slv_number;
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wr_msg.buf = &wbuf[0 + (1 * (!t_slv_params->blockgroupcontrol_valid))];
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wr_msg.addr_page1 = 0x0;
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@@ -981,10 +1019,16 @@ int sdw_compute_sys_interval(struct sdw_bus *sdw_mstr_bs,
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* One port per bus runtime structure
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*/
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/* Calculate sample interval */
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+ t_params->sample_interval =
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+ ((sdw_mstr_bs->clk_freq/
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+ sdw_mstr_bs_rt->stream_params.rate));
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+#else
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t_params->sample_interval =
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((sdw_mstr_bs->clk_freq/
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sdw_mstr_bs_rt->stream_params.rate) * 2);
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+#endif
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/* Only BlockPerPort supported */
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t_params->blockpackingmode = 0;
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t_params->lanecontrol = 0;
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@@ -1106,8 +1150,12 @@ int sdw_compute_hstart_hstop(struct sdw_bus *sdw_mstr_bs, int sel_col)
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*/
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t_params->hstop = hstop;
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+ /* For PDM capture, 0th col is also used */
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+ t_params->hstart = 0;
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+#else
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t_params->hstart = hstop - hwidth + 1;
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-
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+#endif
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/*
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* TBD: perform this when you have 2 ports
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@@ -1234,12 +1282,17 @@ int sdw_compute_blk_subblk_offset(struct sdw_bus *sdw_mstr_bs)
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hstart1 = hstart2 = t_params->hstart;
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hstop1 = hstop2 = t_params->hstop;
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/* TBD: Verify this condition */
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+ block_offset = 1;
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+#else
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block_offset = 0;
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+#endif
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} else {
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hstart1 = t_params->hstart;
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hstop1 = t_params->hstop;
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+#ifndef CONFIG_SND_SOC_SVFPGA
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/* hstart/stop not same */
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if ((hstart1 != hstart2) &&
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(hstop1 != hstop2)) {
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@@ -1249,8 +1302,7 @@ int sdw_compute_blk_subblk_offset(struct sdw_bus *sdw_mstr_bs)
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/* TBD: Harcoding to 0, to be removed*/
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block_offset = 0;
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}
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-
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-#if 0
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+#else
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if ((hstart1 != hstart2) &&
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(hstop1 != hstop2)) {
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block_offset = 1;
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@@ -1481,14 +1533,15 @@ int sdw_cfg_bs_params(struct sdw_bus *sdw_mstr_bs,
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banktouse = !banktouse;
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/*
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- * TBD: Currently harcoded SSP interval to 24,
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+ * TBD: Currently harcoded SSP interval to 50,
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* computed value to be taken from system_interval in
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* bus data structure.
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* Add error check.
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*/
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if (ops->mstr_ops->set_ssp_interval)
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ops->mstr_ops->set_ssp_interval(sdw_mstr_bs->mstr,
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- 24, banktouse); /* hardcoding to 24 */
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+ 50, banktouse);
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+
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/*
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* Configure Clock
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* TBD: Add error check
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--
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https://clearlinux.org
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