34 lines
1.3 KiB
Diff
34 lines
1.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Liu Xinyun <xinyun.liu@intel.com>
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Date: Thu, 31 Oct 2019 19:44:40 +0800
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Subject: [PATCH] drm/i915/gvt: don't update invalid surface address
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Normally 0 belongs to SOS, if plane/pipe is not disabled, SOS screen
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content will be shown on the display screen which is assigned to UOS
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Tracked-On: projectacrn/acrn-hypervisor#3979
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Signed-off-by: Liu Xinyun <xinyun.liu@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/gvt/handlers.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index 9edf8c456dbb..b1cf1ef40ce5 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -2975,7 +2975,8 @@ static int skl_plane_surf_write(struct intel_vgpu *vgpu, unsigned int offset,
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vgpu_vreg_t(vgpu, reg_1ac) = vgpu_vreg(vgpu, offset);
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if ((vgpu_vreg_t(vgpu, PIPECONF(pipe)) & I965_PIPECONF_ACTIVE) &&
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- (vgpu->gvt->pipe_info[pipe].plane_owner[plane] == vgpu->id)) {
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+ (vgpu->gvt->pipe_info[pipe].plane_owner[plane] == vgpu->id) &&
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+ (*(u32 *)p_data != 0)) {
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I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
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}
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--
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https://clearlinux.org
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