53 lines
1.7 KiB
Diff
53 lines
1.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Liu Xinyun <xinyun.liu@intel.com>
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Date: Wed, 24 Apr 2019 17:20:54 +0800
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Subject: [PATCH] drm/i915/gvt: update cursor plane ddb
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Store updated ddb values in the global gvt struct and force update them
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for cursor planes to H/W, even if there is no cursor plane enabled. The
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assumption is the service OS set the ddb topology and calculate the
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watermark based on the plane/pipe information from the guest OS together
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with this fixed ddb values from the service OS.
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v2: merge small patches together
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Tracked-On: projectacrn/acrn-hypervisor#3106
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Signed-off-by: Liu Xinyun <xinyun.liu@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/gvt/gvt.c | 2 ++
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drivers/gpu/drm/i915/intel_pm.c | 4 ++++
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2 files changed, 6 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
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index 9e256a1519ce..89e29b20a538 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.c
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+++ b/drivers/gpu/drm/i915/gvt/gvt.c
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@@ -351,6 +351,8 @@ void intel_gvt_allocate_ddb(struct intel_gvt *gvt,
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ddb->plane[pipe][plane].end =
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ddb->plane[pipe][plane].start + plane_size;
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}
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+
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+ memcpy(&gvt->ddb, ddb, sizeof(*ddb));
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}
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}
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 57a676e8dfe5..c2ff096bd547 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -5650,6 +5650,10 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
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#endif
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}
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+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
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+ skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
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+ &dev_priv->gvt->ddb.plane[pipe][PLANE_CURSOR]);
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+#endif
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return;
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}
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--
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https://clearlinux.org
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