72 lines
2.9 KiB
Diff
72 lines
2.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: qianmenx <qianx.meng@intel.com>
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Date: Mon, 3 Jun 2019 14:15:08 +0800
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Subject: [PATCH] media: intel-ipu4: ox03a10: add metadata support for
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1920x1280
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add metadata support for 1920x1280
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Change-Id: Ie1238a2bdc2881231a0b5807a7b9d54a292c249e
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Depends-on: I13cefd97830916066a6dfe5bd47355fd53c66129
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Tracked-On: PKT-2588
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Tracked-On: #JIIAP-811
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Signed-off-by: qianmenx <qianx.meng@intel.com>
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Signed-off-by: Meng Wei <wei.meng@intel.com>
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---
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.../media/i2c/crlmodule/crl_ox03a10_common.h | 25 ++++++++++++++++++-
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1 file changed, 24 insertions(+), 1 deletion(-)
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diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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index e3bc218826a6..303b379222bb 100644
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--- a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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@@ -174,7 +174,6 @@ static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
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{ 0x3101, CRL_REG_LEN_08BIT, 0x32 },
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{ 0x3192, CRL_REG_LEN_08BIT, 0x00 },
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{ 0x3193, CRL_REG_LEN_08BIT, 0x00 },
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- { 0x3206, CRL_REG_LEN_08BIT, 0x08 },
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{ 0x3216, CRL_REG_LEN_08BIT, 0x01 },
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{ 0x3304, CRL_REG_LEN_08BIT, 0x04 },
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{ 0x3400, CRL_REG_LEN_08BIT, 0x08 },
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@@ -527,6 +526,7 @@ static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
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{ 0x384d, CRL_REG_LEN_08BIT, 0x14 },
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{ 0x460a, CRL_REG_LEN_08BIT, 0x0e },
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/* embedded data */
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+ { 0x3206, CRL_REG_LEN_08BIT, 0x08 },
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{ 0x484c, CRL_REG_LEN_08BIT, 0x02 },
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{ 0x3208, CRL_REG_LEN_08BIT, 0x04 },
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{ 0x483e, CRL_REG_LEN_08BIT, 0x02 },/* frame counter */
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@@ -966,6 +966,29 @@ static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
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{ 0x380d, CRL_REG_LEN_08BIT, 0x7b },
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{ 0x380e, CRL_REG_LEN_08BIT, 0x05 },
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{ 0x380f, CRL_REG_LEN_08BIT, 0x37 },
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+ /* embedded data */
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+ { 0x3206, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x484c, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x3208, CRL_REG_LEN_08BIT, 0x04 },
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+ { 0x483e, CRL_REG_LEN_08BIT, 0x02 },/* frame counter */
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+ { 0x3501, CRL_REG_LEN_08BIT, 0x02 },/* DCG exp */
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+ { 0x3581, CRL_REG_LEN_08BIT, 0x02 },/* VS exp */
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+ { 0x350a, CRL_REG_LEN_08BIT, 0x03 },/* HCG Dgain */
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+ { 0x354a, CRL_REG_LEN_08BIT, 0x03 },/* LCG Dgain */
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+ { 0x358a, CRL_REG_LEN_08BIT, 0x03 },/* VS Dgain */
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+ { 0x3508, CRL_REG_LEN_08BIT, 0x02 },/* HCG Again */
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+ { 0x3548, CRL_REG_LEN_08BIT, 0x02 },/* LCG Again */
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+ { 0x3588, CRL_REG_LEN_08BIT, 0x02 },/* VS Again */
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+ { 0x3208, CRL_REG_LEN_08BIT, 0x14 },
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+ { 0x3208, CRL_REG_LEN_08BIT, 0x05 },
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+ { 0x5000, CRL_REG_LEN_08BIT, 0x10 },
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+ { 0x0304, CRL_REG_LEN_08BIT, 0x19 },
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+ { 0x3208, CRL_REG_LEN_08BIT, 0x15 },
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+ { 0x3217, CRL_REG_LEN_08BIT, 0xbb },
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+ { 0x3219, CRL_REG_LEN_08BIT, 0x55 },
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+ { 0x3216, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x3221, CRL_REG_LEN_08BIT, 0x02 },/* enable CRC */
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+ { 0x366f, CRL_REG_LEN_08BIT, 0xf4 },/* front 2 rows, end 2 rows */
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{ 0x0100, CRL_REG_LEN_08BIT, 0x01 },
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};
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--
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https://clearlinux.org
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