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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Chen Meng J <meng.j.chen@intel.com>
Date: Fri, 31 May 2019 18:20:08 +0800
Subject: [PATCH] media: intel-ipu4: ox03a10: ficosa mode 1920x1280 GRBG12
based on ficosa origin 1920x1280 mode.
- change bayer order to GRBG, ipu supported..
- enable current v4l2 controls.
remove related registers from mode sequence, otherwise it will
overwirte v4l2 controls.
- add SW reset in powerup.
as the set stream sequence: powerup, v4l2 controls, mode.
add SW reset in powerup, reset registers to default for conflict
between modes 1920x1088, 1920x1280, and won't break v4l2 controls.
- PWL mode option C used.
Change-Id: I13cefd97830916066a6dfe5bd47355fd53c66129
Tracked-On: PKT-2588
Tracked-On: #JIIAP-810
Signed-off-by: Chen Meng J <meng.j.chen@intel.com>
Signed-off-by: Meng Wei <wei.meng@intel.com>
---
.../media/i2c/crlmodule/crl_ox03a10_common.h | 26 ++++++-------------
.../i2c/crlmodule/crl_ox03a10_configuration.h | 3 +++
.../crl_ox03a10_ficosa_configuration.h | 3 +++
3 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
index 2d8d67f548f5..7ed721c64730 100644
--- a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
@@ -552,8 +552,6 @@ static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
};
static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
- { 0x0103, CRL_REG_LEN_08BIT, 0x01 },
- { 0x00, CRL_REG_LEN_DELAY, 0x64 }, /* Delay 100 ms */
{ 0x4d07, CRL_REG_LEN_08BIT, 0x21 },
{ 0x4d0e, CRL_REG_LEN_08BIT, 0x80 },
{ 0x4d11, CRL_REG_LEN_08BIT, 0x7d },
@@ -645,10 +643,6 @@ static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
{ 0x3216, CRL_REG_LEN_08BIT, 0x01 },
{ 0x3400, CRL_REG_LEN_08BIT, 0x08 },
{ 0x3409, CRL_REG_LEN_08BIT, 0x02 },
- { 0x3501, CRL_REG_LEN_08BIT, 0x00 },
- { 0x3502, CRL_REG_LEN_08BIT, 0x40 },
- { 0x3581, CRL_REG_LEN_08BIT, 0x00 },
- { 0x3582, CRL_REG_LEN_08BIT, 0x40 },
{ 0x3600, CRL_REG_LEN_08BIT, 0x00 },
{ 0x3602, CRL_REG_LEN_08BIT, 0x42 },
{ 0x3603, CRL_REG_LEN_08BIT, 0xe3 },
@@ -700,7 +694,7 @@ static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
{ 0x3668, CRL_REG_LEN_08BIT, 0x95 },
{ 0x3669, CRL_REG_LEN_08BIT, 0x2c },
{ 0x366f, CRL_REG_LEN_08BIT, 0xc4 },
- { 0x3671, CRL_REG_LEN_08BIT, 0x2f },
+ { 0x3671, CRL_REG_LEN_08BIT, 0x37 },
{ 0x3673, CRL_REG_LEN_08BIT, 0x6a },
{ 0x3674, CRL_REG_LEN_08BIT, 0x32 },
{ 0x3675, CRL_REG_LEN_08BIT, 0x7a },
@@ -708,11 +702,11 @@ static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
{ 0x3800, CRL_REG_LEN_08BIT, 0x00 },
{ 0x3801, CRL_REG_LEN_08BIT, 0x00 },
{ 0x3802, CRL_REG_LEN_08BIT, 0x00 },
- { 0x3803, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x3803, CRL_REG_LEN_08BIT, 0x05 },
{ 0x3804, CRL_REG_LEN_08BIT, 0x07 },
{ 0x3805, CRL_REG_LEN_08BIT, 0x8f },
{ 0x3806, CRL_REG_LEN_08BIT, 0x05 },
- { 0x3807, CRL_REG_LEN_08BIT, 0x0b },
+ { 0x3807, CRL_REG_LEN_08BIT, 0x0c },
{ 0x3808, CRL_REG_LEN_08BIT, 0x07 },
{ 0x3809, CRL_REG_LEN_08BIT, 0x80 },
{ 0x380a, CRL_REG_LEN_08BIT, 0x05 },
@@ -722,11 +716,9 @@ static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
{ 0x380e, CRL_REG_LEN_08BIT, 0x05 },
{ 0x380f, CRL_REG_LEN_08BIT, 0x40 },
{ 0x3810, CRL_REG_LEN_08BIT, 0x00 },
- { 0x3811, CRL_REG_LEN_08BIT, 0x08 },
{ 0x3813, CRL_REG_LEN_08BIT, 0x04 },
{ 0x381c, CRL_REG_LEN_08BIT, 0x00 },
{ 0x3820, CRL_REG_LEN_08BIT, 0x00 },
- { 0x3821, CRL_REG_LEN_08BIT, 0x00 },
{ 0x3822, CRL_REG_LEN_08BIT, 0x14 },
{ 0x3832, CRL_REG_LEN_08BIT, 0x10 },
{ 0x3833, CRL_REG_LEN_08BIT, 0x01 },
@@ -974,13 +966,6 @@ static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
{ 0x380d, CRL_REG_LEN_08BIT, 0x90 },
{ 0x380e, CRL_REG_LEN_08BIT, 0x05 },
{ 0x380f, CRL_REG_LEN_08BIT, 0x37 },
- { 0x3501, CRL_REG_LEN_08BIT, 0x03 },
- { 0x3502, CRL_REG_LEN_08BIT, 0x21 },
- { 0x3508, CRL_REG_LEN_08BIT, 0x04 },
- { 0x3548, CRL_REG_LEN_08BIT, 0x01 },
- { 0x3549, CRL_REG_LEN_08BIT, 0xa0 },
- { 0x354a, CRL_REG_LEN_08BIT, 0x01 },
- { 0x354b, CRL_REG_LEN_08BIT, 0x20 },
{ 0x0100, CRL_REG_LEN_08BIT, 0x01 },
};
@@ -2083,6 +2068,11 @@ static struct crl_register_write_rep ox03a10_streamoff_regs[] = {
{ 0x0100, CRL_REG_LEN_08BIT, 0x00 }
};
+static struct crl_register_write_rep ox03a10_powerup_regs[] = {
+ { 0x0103, CRL_REG_LEN_08BIT, 0x01 }, /* software reset */
+ { 0x00, CRL_REG_LEN_DELAY, 0x64 } /* Delay 100 ms */
+};
+
static struct crl_arithmetic_ops ox03a10_frame_desc_width_ops[] = {
{
.op = CRL_ASSIGNMENT,
diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h b/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h
index cb2c89cbfb9b..63e86480b813 100644
--- a/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h
+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h
@@ -49,6 +49,9 @@ struct crl_sensor_configuration ox03a10_crl_configuration = {
.streamoff_regs_items = ARRAY_SIZE(ox03a10_streamoff_regs),
.streamoff_regs = ox03a10_streamoff_regs,
+ .powerup_regs_items = ARRAY_SIZE(ox03a10_powerup_regs),
+ .powerup_regs = ox03a10_powerup_regs,
+
.frame_desc_entries = ARRAY_SIZE(ox03a10_frame_desc),
.frame_desc_type = CRL_V4L2_MBUS_FRAME_DESC_TYPE_CSI2,
.frame_desc = ox03a10_frame_desc,
diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h b/drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h
index eaf262852608..a52462341770 100644
--- a/drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h
+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h
@@ -49,6 +49,9 @@ struct crl_sensor_configuration ox03a10_ficosa_crl_configuration = {
.streamoff_regs_items = ARRAY_SIZE(ox03a10_streamoff_regs),
.streamoff_regs = ox03a10_streamoff_regs,
+ .powerup_regs_items = ARRAY_SIZE(ox03a10_powerup_regs),
+ .powerup_regs = ox03a10_powerup_regs,
+
.frame_desc_entries = ARRAY_SIZE(ox03a10_frame_desc),
.frame_desc_type = CRL_V4L2_MBUS_FRAME_DESC_TYPE_CSI2,
.frame_desc = ox03a10_frame_desc,
--
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