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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Chen Meng J <meng.j.chen@intel.com>
Date: Fri, 31 May 2019 18:15:53 +0800
Subject: [PATCH] media: intel-ipu4: ox03a10: ficosa original mode 1920x1280
ficosa original mode 1920x1280.
Change-Id: Id077571fa6114ffee98d92f83a9f15da07e61e53
Tracked-On: PKT-2588
Tracked-On: #JIIAP-810
Signed-off-by: Chen Meng J <meng.j.chen@intel.com>
Signed-off-by: Meng Wei <wei.meng@intel.com>
---
.../media/i2c/crlmodule/crl_ox03a10_common.h | 454 +++++++++++++++++-
1 file changed, 452 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
index 484e89526226..2d8d67f548f5 100644
--- a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
@@ -551,6 +551,439 @@ static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
{ 0x0100, CRL_REG_LEN_08BIT, 0x01 },
};
+static struct crl_register_write_rep ox03a10_1920_1280_12DCG[] = {
+ { 0x0103, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x00, CRL_REG_LEN_DELAY, 0x64 }, /* Delay 100 ms */
+ { 0x4d07, CRL_REG_LEN_08BIT, 0x21 },
+ { 0x4d0e, CRL_REG_LEN_08BIT, 0x80 },
+ { 0x4d11, CRL_REG_LEN_08BIT, 0x7d },
+ { 0x0303, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x0304, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0305, CRL_REG_LEN_08BIT, 0x34 },
+ { 0x0306, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x0307, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0308, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x0309, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x030C, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0316, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0317, CRL_REG_LEN_08BIT, 0x42 },
+ { 0x0322, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0323, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x0325, CRL_REG_LEN_08BIT, 0x68 },
+ { 0x0326, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0327, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x0328, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x0329, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x032a, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x032b, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0400, CRL_REG_LEN_08BIT, 0xe8 },
+ { 0x0401, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0404, CRL_REG_LEN_08BIT, 0x2b },
+ { 0x0405, CRL_REG_LEN_08BIT, 0x32 },
+ { 0x0406, CRL_REG_LEN_08BIT, 0x35 },
+ { 0x0407, CRL_REG_LEN_08BIT, 0x8a },
+ { 0x0408, CRL_REG_LEN_08BIT, 0x0c },
+ { 0x0410, CRL_REG_LEN_08BIT, 0xe8 },
+ { 0x0411, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x0414, CRL_REG_LEN_08BIT, 0x2b },
+ { 0x0415, CRL_REG_LEN_08BIT, 0x32 },
+ { 0x0416, CRL_REG_LEN_08BIT, 0x35 },
+ { 0x0417, CRL_REG_LEN_08BIT, 0x8a },
+ { 0x0418, CRL_REG_LEN_08BIT, 0x0c },
+ { 0x3002, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x3012, CRL_REG_LEN_08BIT, 0x41 },
+ { 0x301e, CRL_REG_LEN_08BIT, 0xb0 },
+ { 0x3706, CRL_REG_LEN_08BIT, 0x39 },
+ { 0x370a, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x370b, CRL_REG_LEN_08BIT, 0xa3 },
+ { 0x3712, CRL_REG_LEN_08BIT, 0x12 },
+ { 0x3713, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x372c, CRL_REG_LEN_08BIT, 0x17 },
+ { 0x3733, CRL_REG_LEN_08BIT, 0x41 },
+ { 0x3741, CRL_REG_LEN_08BIT, 0x44 },
+ { 0x3742, CRL_REG_LEN_08BIT, 0x34 },
+ { 0x3746, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x374b, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x3755, CRL_REG_LEN_08BIT, 0x09 },
+ { 0x376c, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x376d, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x376f, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x3770, CRL_REG_LEN_08BIT, 0x91 },
+ { 0x3771, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x3774, CRL_REG_LEN_08BIT, 0x8a },
+ { 0x3777, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3779, CRL_REG_LEN_08BIT, 0x22 },
+ { 0x377a, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x377b, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x377c, CRL_REG_LEN_08BIT, 0x48 },
+ { 0x3785, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x3790, CRL_REG_LEN_08BIT, 0x10 },
+ { 0x3793, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x379c, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x37a1, CRL_REG_LEN_08BIT, 0x80 },
+ { 0x37b3, CRL_REG_LEN_08BIT, 0x0a },
+ { 0x37be, CRL_REG_LEN_08BIT, 0x10 },
+ { 0x37bf, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x37c6, CRL_REG_LEN_08BIT, 0x48 },
+ { 0x37c7, CRL_REG_LEN_08BIT, 0x38 },
+ { 0x37c9, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x37ca, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x37cb, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x37cc, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x37d1, CRL_REG_LEN_08BIT, 0x39 },
+ { 0x37d2, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x37d3, CRL_REG_LEN_08BIT, 0xa3 },
+ { 0x37d5, CRL_REG_LEN_08BIT, 0x39 },
+ { 0x37d6, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x37d7, CRL_REG_LEN_08BIT, 0xa3 },
+ { 0x3c06, CRL_REG_LEN_08BIT, 0x29 },
+ { 0x3c0b, CRL_REG_LEN_08BIT, 0xa8 },
+ { 0x3c53, CRL_REG_LEN_08BIT, 0x68 },
+ { 0x3192, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3193, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3206, CRL_REG_LEN_08BIT, 0x80 },
+ { 0x3216, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x3400, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x3409, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x3501, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3502, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3581, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3582, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3600, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3602, CRL_REG_LEN_08BIT, 0x42 },
+ { 0x3603, CRL_REG_LEN_08BIT, 0xe3 },
+ { 0x3604, CRL_REG_LEN_08BIT, 0x93 },
+ { 0x3605, CRL_REG_LEN_08BIT, 0xff },
+ { 0x3606, CRL_REG_LEN_08BIT, 0xc0 },
+ { 0x3607, CRL_REG_LEN_08BIT, 0x4a },
+ { 0x360a, CRL_REG_LEN_08BIT, 0xd0 },
+ { 0x360b, CRL_REG_LEN_08BIT, 0x0b },
+ { 0x360e, CRL_REG_LEN_08BIT, 0x88 },
+ { 0x3611, CRL_REG_LEN_08BIT, 0x4b },
+ { 0x3612, CRL_REG_LEN_08BIT, 0x4e },
+ { 0x3619, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3620, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x3626, CRL_REG_LEN_08BIT, 0x0e },
+ { 0x362c, CRL_REG_LEN_08BIT, 0x0e },
+ { 0x362d, CRL_REG_LEN_08BIT, 0x12 },
+ { 0x362e, CRL_REG_LEN_08BIT, 0x0b },
+ { 0x362f, CRL_REG_LEN_08BIT, 0x18 },
+ { 0x3630, CRL_REG_LEN_08BIT, 0x30 },
+ { 0x3631, CRL_REG_LEN_08BIT, 0x57 },
+ { 0x3632, CRL_REG_LEN_08BIT, 0x99 },
+ { 0x3633, CRL_REG_LEN_08BIT, 0x99 },
+ { 0x3643, CRL_REG_LEN_08BIT, 0x0c },
+ { 0x3644, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3645, CRL_REG_LEN_08BIT, 0x0e },
+ { 0x3646, CRL_REG_LEN_08BIT, 0x0f },
+ { 0x3647, CRL_REG_LEN_08BIT, 0x0e },
+ { 0x3648, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3649, CRL_REG_LEN_08BIT, 0x11 },
+ { 0x364a, CRL_REG_LEN_08BIT, 0x12 },
+ { 0x364c, CRL_REG_LEN_08BIT, 0x0e },
+ { 0x364d, CRL_REG_LEN_08BIT, 0x0e },
+ { 0x364e, CRL_REG_LEN_08BIT, 0x12 },
+ { 0x364f, CRL_REG_LEN_08BIT, 0x0e },
+ { 0x3652, CRL_REG_LEN_08BIT, 0xc5 },
+ { 0x3657, CRL_REG_LEN_08BIT, 0x88 },
+ { 0x3658, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x365a, CRL_REG_LEN_08BIT, 0x57 },
+ { 0x365b, CRL_REG_LEN_08BIT, 0x30 },
+ { 0x365c, CRL_REG_LEN_08BIT, 0x18 },
+ { 0x365d, CRL_REG_LEN_08BIT, 0x0b },
+ { 0x3660, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x3661, CRL_REG_LEN_08BIT, 0x07 },
+ { 0x3662, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3665, CRL_REG_LEN_08BIT, 0x92 },
+ { 0x3666, CRL_REG_LEN_08BIT, 0x13 },
+ { 0x3667, CRL_REG_LEN_08BIT, 0x2c },
+ { 0x3668, CRL_REG_LEN_08BIT, 0x95 },
+ { 0x3669, CRL_REG_LEN_08BIT, 0x2c },
+ { 0x366f, CRL_REG_LEN_08BIT, 0xc4 },
+ { 0x3671, CRL_REG_LEN_08BIT, 0x2f },
+ { 0x3673, CRL_REG_LEN_08BIT, 0x6a },
+ { 0x3674, CRL_REG_LEN_08BIT, 0x32 },
+ { 0x3675, CRL_REG_LEN_08BIT, 0x7a },
+ { 0x3678, CRL_REG_LEN_08BIT, 0x88 },
+ { 0x3800, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3801, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3802, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3803, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x3804, CRL_REG_LEN_08BIT, 0x07 },
+ { 0x3805, CRL_REG_LEN_08BIT, 0x8f },
+ { 0x3806, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x3807, CRL_REG_LEN_08BIT, 0x0b },
+ { 0x3808, CRL_REG_LEN_08BIT, 0x07 },
+ { 0x3809, CRL_REG_LEN_08BIT, 0x80 },
+ { 0x380a, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x380b, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x380c, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x380d, CRL_REG_LEN_08BIT, 0x14 },
+ { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x380f, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3810, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3811, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x3813, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x381c, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3820, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3821, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3822, CRL_REG_LEN_08BIT, 0x14 },
+ { 0x3832, CRL_REG_LEN_08BIT, 0x10 },
+ { 0x3833, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x3834, CRL_REG_LEN_08BIT, 0xf0 },
+ { 0x383d, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x384c, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x384d, CRL_REG_LEN_08BIT, 0x14 },
+ { 0x384e, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x384f, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3850, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3851, CRL_REG_LEN_08BIT, 0x42 },
+ { 0x3852, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3853, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3854, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3855, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x3856, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x3857, CRL_REG_LEN_08BIT, 0x33 },
+ { 0x3858, CRL_REG_LEN_08BIT, 0x3c },
+ { 0x3859, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x385a, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x385b, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x385c, CRL_REG_LEN_08BIT, 0x32 },
+ { 0x385f, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3860, CRL_REG_LEN_08BIT, 0x10 },
+ { 0x3861, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3862, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3863, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3864, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3865, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3866, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x3b40, CRL_REG_LEN_08BIT, 0x3e },
+ { 0x3b41, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b42, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x3b43, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b44, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b45, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x3b46, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b47, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x3b84, CRL_REG_LEN_08BIT, 0x36 },
+ { 0x3b85, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b86, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b87, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x3b88, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b89, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x3b8a, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x3b8b, CRL_REG_LEN_08BIT, 0x0a },
+ { 0x3b8e, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x3b8f, CRL_REG_LEN_08BIT, 0xe8 },
+ { 0x3d85, CRL_REG_LEN_08BIT, 0x0b },
+ { 0x3d8c, CRL_REG_LEN_08BIT, 0x70 },
+ { 0x3d8d, CRL_REG_LEN_08BIT, 0x26 },
+ { 0x3d97, CRL_REG_LEN_08BIT, 0x70 },
+ { 0x3d98, CRL_REG_LEN_08BIT, 0x24 },
+ { 0x3d99, CRL_REG_LEN_08BIT, 0x70 },
+ { 0x3d9a, CRL_REG_LEN_08BIT, 0x6d },
+ { 0x3d9b, CRL_REG_LEN_08BIT, 0x70 },
+ { 0x3d9c, CRL_REG_LEN_08BIT, 0x6e },
+ { 0x3d9d, CRL_REG_LEN_08BIT, 0x73 },
+ { 0x3d9e, CRL_REG_LEN_08BIT, 0xff },
+ { 0x3f00, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x4001, CRL_REG_LEN_08BIT, 0x2b },
+ { 0x4004, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x4005, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x4008, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x4009, CRL_REG_LEN_08BIT, 0x0d },
+ { 0x400a, CRL_REG_LEN_08BIT, 0x08 },
+ { 0x400b, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x400f, CRL_REG_LEN_08BIT, 0x80 },
+ { 0x4010, CRL_REG_LEN_08BIT, 0x10 },
+ { 0x4016, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x4017, CRL_REG_LEN_08BIT, 0x10 },
+ { 0x402e, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x402f, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x4030, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x4031, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x4032, CRL_REG_LEN_08BIT, 0x9f },
+ { 0x4033, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x4308, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x4502, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x4507, CRL_REG_LEN_08BIT, 0x16 },
+ { 0x4580, CRL_REG_LEN_08BIT, 0xf8 },
+ { 0x4602, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x4603, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x460a, CRL_REG_LEN_08BIT, 0x36 },
+ { 0x460c, CRL_REG_LEN_08BIT, 0x60 },
+ { 0x4800, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x480e, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x4813, CRL_REG_LEN_08BIT, 0x12 },
+ { 0x4815, CRL_REG_LEN_08BIT, 0x2b },
+ { 0x4837, CRL_REG_LEN_08BIT, 0x12 },
+ { 0x484b, CRL_REG_LEN_08BIT, 0x27 },
+ { 0x484c, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x4886, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x4903, CRL_REG_LEN_08BIT, 0x80 },
+ { 0x4f00, CRL_REG_LEN_08BIT, 0xff },
+ { 0x4f01, CRL_REG_LEN_08BIT, 0xff },
+ { 0x4f05, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x5180, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x5181, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5182, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x5183, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5184, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x5185, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5186, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x5187, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51a0, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51a1, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51a2, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51a3, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51a4, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51a5, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51a6, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51a7, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51c0, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51c1, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51c2, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51c3, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51c4, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51c5, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x51c6, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x51c7, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5380, CRL_REG_LEN_08BIT, 0x19 },
+ { 0x5382, CRL_REG_LEN_08BIT, 0x2e },
+ { 0x53a0, CRL_REG_LEN_08BIT, 0x41 },
+ { 0x53a2, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x53a3, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x53a4, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x53a5, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x53a7, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5400, CRL_REG_LEN_08BIT, 0x19 },
+ { 0x5402, CRL_REG_LEN_08BIT, 0x2e },
+ { 0x5420, CRL_REG_LEN_08BIT, 0x41 },
+ { 0x5422, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x5423, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5424, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x5425, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5427, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5480, CRL_REG_LEN_08BIT, 0x19 },
+ { 0x5482, CRL_REG_LEN_08BIT, 0x2e },
+ { 0x54a0, CRL_REG_LEN_08BIT, 0x41 },
+ { 0x54a2, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x54a3, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x54a4, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x54a5, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x54a7, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5800, CRL_REG_LEN_08BIT, 0x38 },
+ { 0x5801, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5802, CRL_REG_LEN_08BIT, 0xc0 },
+ { 0x5804, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5805, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x5806, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x5807, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x580e, CRL_REG_LEN_08BIT, 0x10 },
+ { 0x5812, CRL_REG_LEN_08BIT, 0x34 },
+ { 0x5000, CRL_REG_LEN_08BIT, 0x89 },
+ { 0x5001, CRL_REG_LEN_08BIT, 0x42 },
+ { 0x5002, CRL_REG_LEN_08BIT, 0x39 },
+ { 0x5003, CRL_REG_LEN_08BIT, 0x16 },
+ { 0x5004, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5005, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x5006, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5007, CRL_REG_LEN_08BIT, 0x40 },
+ { 0x503e, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x503f, CRL_REG_LEN_08BIT, 0x00 },
+ { 0x5602, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5603, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5604, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5605, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5606, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5607, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5608, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5609, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x560a, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x560b, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x560c, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x560d, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x560e, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x560f, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5610, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5611, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5612, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5613, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5614, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5615, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5616, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5617, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5618, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5619, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5642, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5643, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5644, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5645, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5646, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5647, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5648, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5649, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x564a, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x564b, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x564c, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x564d, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x564e, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x564f, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5650, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5651, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5652, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5653, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5654, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5655, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5656, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5657, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5658, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5659, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5682, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5683, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5684, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5685, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5686, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5687, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5688, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5689, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x568a, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x568b, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x568c, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x568d, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x568e, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x568f, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5690, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5691, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5692, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5693, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5694, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5695, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5696, CRL_REG_LEN_08BIT, 0x02 },
+ { 0x5697, CRL_REG_LEN_08BIT, 0x58 },
+ { 0x5698, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x5699, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x5709, CRL_REG_LEN_08BIT, 0x0f },
+ { 0x5749, CRL_REG_LEN_08BIT, 0x0f },
+ { 0x5789, CRL_REG_LEN_08BIT, 0x0f },
+ { 0x5200, CRL_REG_LEN_08BIT, 0x70 },
+ { 0x5201, CRL_REG_LEN_08BIT, 0x70 },
+ { 0x5202, CRL_REG_LEN_08BIT, 0x73 },
+ { 0x5203, CRL_REG_LEN_08BIT, 0xff },
+ { 0x380c, CRL_REG_LEN_08BIT, 0x0a },
+ { 0x380d, CRL_REG_LEN_08BIT, 0x90 },
+ { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
+ { 0x380f, CRL_REG_LEN_08BIT, 0x37 },
+ { 0x3501, CRL_REG_LEN_08BIT, 0x03 },
+ { 0x3502, CRL_REG_LEN_08BIT, 0x21 },
+ { 0x3508, CRL_REG_LEN_08BIT, 0x04 },
+ { 0x3548, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x3549, CRL_REG_LEN_08BIT, 0xa0 },
+ { 0x354a, CRL_REG_LEN_08BIT, 0x01 },
+ { 0x354b, CRL_REG_LEN_08BIT, 0x20 },
+ { 0x0100, CRL_REG_LEN_08BIT, 0x01 },
+};
+
static struct crl_register_write_rep ox03a10_1920_1088_12DCG_12VS[] = {
{ 0x4d09, CRL_REG_LEN_08BIT, 0x5f },
{ 0x0104, CRL_REG_LEN_08BIT, 0x04 },
@@ -1015,6 +1448,10 @@ struct crl_ctrl_data_pair ox03a10_ctrl_data_modes[] = {
{
.ctrl_id = CRL_CID_EXPOSURE_MODE,
.data = 1,
+ },
+ {
+ .ctrl_id = CRL_CID_EXPOSURE_MODE,
+ .data = 2,
}
};
@@ -1495,7 +1932,7 @@ struct crl_v4l2_ctrl ox03a10_v4l2_ctrls[] = {
.ctrl_id = CRL_CID_EXPOSURE_MODE,
.type = CRL_V4L2_CTRL_TYPE_CUSTOM,
.data.std_data.min = 0,
- .data.std_data.max = 1,
+ .data.std_data.max = 2,
.data.std_data.step = 1,
.data.std_data.def = 0,
.flags = V4L2_CTRL_FLAG_UPDATE,
@@ -1707,7 +2144,7 @@ struct crl_sensor_limits ox03a10_sensor_limits = {
.x_addr_min = 0,
.y_addr_min = 0,
.x_addr_max = 1920,
- .y_addr_max = 1088,
+ .y_addr_max = 1280,
};
struct crl_mode_rep ox03a10_modes[] = {
@@ -1737,6 +2174,19 @@ struct crl_mode_rep ox03a10_modes[] = {
.mode_regs_items = ARRAY_SIZE(ox03a10_1920_1088_12DCG_12VS),
.mode_regs = ox03a10_1920_1088_12DCG_12VS,
},
+ {
+ .sd_rects_items = ARRAY_SIZE(ox03a10_1920_1280_rects),
+ .sd_rects = ox03a10_1920_1280_rects,
+ .binn_hor = 1,
+ .binn_vert = 1,
+ .scale_m = 1,
+ .width = 1920,
+ .height = 1280,
+ .comp_items = 1,
+ .ctrl_data = &ox03a10_ctrl_data_modes[2],
+ .mode_regs_items = ARRAY_SIZE(ox03a10_1920_1280_12DCG),
+ .mode_regs = ox03a10_1920_1280_12DCG,
+ },
};
#endif /* __CRLMODULE_OX03A10_COMMON_H_ */
--
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