3483 lines
112 KiB
Diff
3483 lines
112 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Chen Meng J <meng.j.chen@intel.com>
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Date: Tue, 26 Mar 2019 11:17:35 +0800
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Subject: [PATCH] media: intel-ipu4: ox03a10: add ficosa module
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add a different module ficosa of sensor ox03a10
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Change-Id: Id643efa345da814e0602ed04014abc26e4d62a23
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Tracked-On: PKT-2588
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Tracked-On: #JIIAP-736
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Signed-off-by: Chen Meng J <meng.j.chen@intel.com>
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Signed-off-by: Meng Wei <wei.meng@intel.com>
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---
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.../media/i2c/crlmodule/crl_ox03a10_common.h | 1696 +++++++++++++++++
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.../i2c/crlmodule/crl_ox03a10_configuration.h | 1654 +---------------
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.../crl_ox03a10_ficosa_configuration.h | 57 +
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drivers/media/i2c/crlmodule/crlmodule-data.c | 3 +
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4 files changed, 1757 insertions(+), 1653 deletions(-)
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create mode 100644 drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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create mode 100644 drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h
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diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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new file mode 100644
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index 000000000000..7ef243bcdcb0
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--- /dev/null
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+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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@@ -0,0 +1,1696 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/* Copyright (C) 2019 Intel Corporation
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+ *
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+ * Author: Chang Ying <ying.chang@intel.com>
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+ *
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+ */
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+
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+#ifndef __CRLMODULE_OX03A10_COMMON_H_
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+#define __CRLMODULE_OX03A10_COMMON_H_
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+
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+#include "crlmodule-sensor-ds.h"
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+
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+struct crl_sensor_detect_config ox03a10_sensor_detect_regset[] = {
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+ {
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+ .reg = {0x300A, CRL_REG_LEN_08BIT, 0x58},
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+ .width = 12,
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+ },
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+ {
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+ .reg = {0x300B, CRL_REG_LEN_08BIT, 0x03},
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+ .width = 12,
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+ },
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+ {
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+ .reg = {0x300C, CRL_REG_LEN_08BIT, 0x41},
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+ .width = 12,
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+ }
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+};
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+
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+struct crl_subdev_rect_rep ox03a10_1920_1088_rects[] = {
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
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+ .in_rect.left = 0,
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+ .in_rect.top = 0,
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+ .in_rect.width = 1920,
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+ .in_rect.height = 1088,
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+ .out_rect.left = 0,
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+ .out_rect.top = 0,
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+ .out_rect.width = 1920,
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+ .out_rect.height = 1088,
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+ },
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_BINNER,
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+ .in_rect.left = 0,
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+ .in_rect.top = 0,
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+ .in_rect.width = 1920,
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+ .in_rect.height = 1088,
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+ .out_rect.left = 0,
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+ .out_rect.top = 0,
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+ .out_rect.width = 1920,
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+ .out_rect.height = 1088,
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+ }
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+};
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+
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+struct crl_subdev_rect_rep ox03a10_1920_1280_rects[] = {
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
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+ .in_rect.left = 0,
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+ .in_rect.top = 0,
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+ .in_rect.width = 1920,
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+ .in_rect.height = 1280,
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+ .out_rect.left = 0,
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+ .out_rect.top = 0,
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+ .out_rect.width = 1920,
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+ .out_rect.height = 1280,
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+ },
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_BINNER,
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+ .in_rect.left = 0,
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+ .in_rect.top = 0,
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+ .in_rect.width = 1920,
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+ .in_rect.height = 1280,
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+ .out_rect.left = 0,
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+ .out_rect.top = 0,
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+ .out_rect.width = 1920,
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+ .out_rect.height = 1280,
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+ }
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+};
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+
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+static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
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+ { 0x4d09, CRL_REG_LEN_08BIT, 0x5f },
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+ { 0x0104, CRL_REG_LEN_08BIT, 0x04 },
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+ { 0x0303, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x0305, CRL_REG_LEN_08BIT, 0x32 },
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+ { 0x0307, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x0316, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x0317, CRL_REG_LEN_08BIT, 0x12 },
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+ { 0x0323, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x0325, CRL_REG_LEN_08BIT, 0x6c },
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+ { 0x0326, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x032b, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x0400, CRL_REG_LEN_08BIT, 0xe7 },
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+ { 0x0401, CRL_REG_LEN_08BIT, 0xff },
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+ { 0x0404, CRL_REG_LEN_08BIT, 0x2b },
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+ { 0x0405, CRL_REG_LEN_08BIT, 0x32 },
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+ { 0x0406, CRL_REG_LEN_08BIT, 0x33 },
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+ { 0x0407, CRL_REG_LEN_08BIT, 0x8f },
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+ { 0x0408, CRL_REG_LEN_08BIT, 0x0c },
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+ { 0x0410, CRL_REG_LEN_08BIT, 0xe7 },
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+ { 0x0411, CRL_REG_LEN_08BIT, 0xff },
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+ { 0x0414, CRL_REG_LEN_08BIT, 0x2b },
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+ { 0x0415, CRL_REG_LEN_08BIT, 0x32 },
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+ { 0x0416, CRL_REG_LEN_08BIT, 0x33 },
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+ { 0x0417, CRL_REG_LEN_08BIT, 0x8f },
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+ { 0x0418, CRL_REG_LEN_08BIT, 0x0c },
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+ { 0x3002, CRL_REG_LEN_08BIT, 0x03 },
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+ { 0x3012, CRL_REG_LEN_08BIT, 0x41 },
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+ { 0x3016, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x3017, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x3018, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x3019, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x301a, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x301b, CRL_REG_LEN_08BIT, 0xb4 },
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+ { 0x301e, CRL_REG_LEN_08BIT, 0xb8 },
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+ { 0x301f, CRL_REG_LEN_08BIT, 0xe1 },
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+ { 0x3022, CRL_REG_LEN_08BIT, 0xf8 },
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+ { 0x3023, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x3024, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x3028, CRL_REG_LEN_08BIT, 0xf0 },
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+ { 0x3029, CRL_REG_LEN_08BIT, 0x80 },
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+ { 0x3706, CRL_REG_LEN_08BIT, 0x39 },
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+ { 0x370a, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x370b, CRL_REG_LEN_08BIT, 0xa3 },
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+ { 0x3712, CRL_REG_LEN_08BIT, 0x12 },
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+ { 0x3713, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3716, CRL_REG_LEN_08BIT, 0x04 },
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+ { 0x371d, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x3721, CRL_REG_LEN_08BIT, 0x1c },
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+ { 0x372c, CRL_REG_LEN_08BIT, 0x17 },
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+ { 0x3733, CRL_REG_LEN_08BIT, 0x41 },
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+ { 0x3741, CRL_REG_LEN_08BIT, 0x44 },
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+ { 0x3742, CRL_REG_LEN_08BIT, 0x34 },
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+ { 0x3746, CRL_REG_LEN_08BIT, 0x03 },
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+ { 0x374b, CRL_REG_LEN_08BIT, 0x03 },
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+ { 0x3755, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x376c, CRL_REG_LEN_08BIT, 0x15 },
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+ { 0x376d, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x376f, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x3770, CRL_REG_LEN_08BIT, 0x91 },
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+ { 0x3771, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x3774, CRL_REG_LEN_08BIT, 0x82 },
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+ { 0x3777, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3779, CRL_REG_LEN_08BIT, 0x22 },
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+ { 0x377a, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x377b, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x377c, CRL_REG_LEN_08BIT, 0x48 },
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+ { 0x3785, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x3790, CRL_REG_LEN_08BIT, 0x10 },
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+ { 0x3793, CRL_REG_LEN_08BIT, 0x04 },
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+ { 0x379c, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x37a1, CRL_REG_LEN_08BIT, 0x80 },
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+ { 0x37b3, CRL_REG_LEN_08BIT, 0x0a },
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+ { 0x37bb, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x37be, CRL_REG_LEN_08BIT, 0xe0 },
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+ { 0x37bf, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x37c6, CRL_REG_LEN_08BIT, 0x48 },
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+ { 0x37c7, CRL_REG_LEN_08BIT, 0x38 },
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+ { 0x37c9, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x37ca, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x37cb, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x37cc, CRL_REG_LEN_08BIT, 0x40 },
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+ { 0x37d1, CRL_REG_LEN_08BIT, 0x39 },
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+ { 0x37d2, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x37d3, CRL_REG_LEN_08BIT, 0xa3 },
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+ { 0x37d5, CRL_REG_LEN_08BIT, 0x39 },
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+ { 0x37d6, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x37d7, CRL_REG_LEN_08BIT, 0xa3 },
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+ { 0x3c06, CRL_REG_LEN_08BIT, 0x29 },
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+ { 0x3c0b, CRL_REG_LEN_08BIT, 0xa8 },
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+ { 0x3c12, CRL_REG_LEN_08BIT, 0x89 },
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+ { 0x3c14, CRL_REG_LEN_08BIT, 0x81 },
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+ { 0x3c18, CRL_REG_LEN_08BIT, 0x0c },
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+ { 0x3c3b, CRL_REG_LEN_08BIT, 0x38 },
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+ { 0x3c53, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x3c55, CRL_REG_LEN_08BIT, 0xeb },
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+ { 0x3101, CRL_REG_LEN_08BIT, 0x32 },
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+ { 0x3192, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3193, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3206, CRL_REG_LEN_08BIT, 0xc8 },
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+ { 0x3216, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x3304, CRL_REG_LEN_08BIT, 0x04 },
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+ { 0x3400, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x3409, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x3600, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3601, CRL_REG_LEN_08BIT, 0x70 },
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+ { 0x3602, CRL_REG_LEN_08BIT, 0x42 },
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+ { 0x3603, CRL_REG_LEN_08BIT, 0xe3 },
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+ { 0x3604, CRL_REG_LEN_08BIT, 0x93 },
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+ { 0x3605, CRL_REG_LEN_08BIT, 0xff },
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+ { 0x3606, CRL_REG_LEN_08BIT, 0x80 },
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+ { 0x3607, CRL_REG_LEN_08BIT, 0x4a },
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+ { 0x3608, CRL_REG_LEN_08BIT, 0x98 },
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+ { 0x3609, CRL_REG_LEN_08BIT, 0x70 },
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+ { 0x360a, CRL_REG_LEN_08BIT, 0x90 },
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+ { 0x360b, CRL_REG_LEN_08BIT, 0x0a },
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+ { 0x360e, CRL_REG_LEN_08BIT, 0x88 },
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+ { 0x3610, CRL_REG_LEN_08BIT, 0x89 },
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+ { 0x3611, CRL_REG_LEN_08BIT, 0x4b },
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+ { 0x3612, CRL_REG_LEN_08BIT, 0x4e },
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+ { 0x3619, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3620, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x3621, CRL_REG_LEN_08BIT, 0x80 },
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+ { 0x3626, CRL_REG_LEN_08BIT, 0x0e },
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+ { 0x362c, CRL_REG_LEN_08BIT, 0x0e },
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+ { 0x362d, CRL_REG_LEN_08BIT, 0x12 },
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+ { 0x362e, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x362f, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3630, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3631, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3632, CRL_REG_LEN_08BIT, 0x99 },
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+ { 0x3633, CRL_REG_LEN_08BIT, 0x99 },
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+ { 0x3643, CRL_REG_LEN_08BIT, 0x0c },
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+ { 0x3644, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3645, CRL_REG_LEN_08BIT, 0x0e },
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+ { 0x3646, CRL_REG_LEN_08BIT, 0x0f },
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+ { 0x3647, CRL_REG_LEN_08BIT, 0x0e },
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+ { 0x3648, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3649, CRL_REG_LEN_08BIT, 0x11 },
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+ { 0x364a, CRL_REG_LEN_08BIT, 0x12 },
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+ { 0x364c, CRL_REG_LEN_08BIT, 0x0e },
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+ { 0x364d, CRL_REG_LEN_08BIT, 0x0e },
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+ { 0x364e, CRL_REG_LEN_08BIT, 0x12 },
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+ { 0x364f, CRL_REG_LEN_08BIT, 0x0e },
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+ { 0x3652, CRL_REG_LEN_08BIT, 0xc5 },
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+ { 0x3654, CRL_REG_LEN_08BIT, 0x40 },
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+ { 0x3656, CRL_REG_LEN_08BIT, 0xcf },
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+ { 0x3657, CRL_REG_LEN_08BIT, 0x88 },
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+ { 0x3658, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x365a, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x365b, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x365c, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x365d, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3660, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x3661, CRL_REG_LEN_08BIT, 0x07 },
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+ { 0x3662, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3663, CRL_REG_LEN_08BIT, 0x20 },
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+ { 0x3665, CRL_REG_LEN_08BIT, 0x12 },
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+ { 0x3666, CRL_REG_LEN_08BIT, 0x13 },
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+ { 0x3667, CRL_REG_LEN_08BIT, 0x14 },
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+ { 0x3668, CRL_REG_LEN_08BIT, 0x95 },
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+ { 0x3669, CRL_REG_LEN_08BIT, 0x16 },
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+ { 0x366f, CRL_REG_LEN_08BIT, 0xc4 },
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+ { 0x3671, CRL_REG_LEN_08BIT, 0x37 },
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+ { 0x3673, CRL_REG_LEN_08BIT, 0x6a },
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+ { 0x3678, CRL_REG_LEN_08BIT, 0x88 },
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+ { 0x3800, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3801, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3802, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3803, CRL_REG_LEN_08BIT, 0x05 },
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+ { 0x3804, CRL_REG_LEN_08BIT, 0x07 },
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+ { 0x3805, CRL_REG_LEN_08BIT, 0x8f },
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+ { 0x3806, CRL_REG_LEN_08BIT, 0x05 },
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+ { 0x3807, CRL_REG_LEN_08BIT, 0x0c },
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+ { 0x3808, CRL_REG_LEN_08BIT, 0x07 },
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+ { 0x3809, CRL_REG_LEN_08BIT, 0x80 },
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+ { 0x380a, CRL_REG_LEN_08BIT, 0x04 },
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+ { 0x380b, CRL_REG_LEN_08BIT, 0x40 },
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+ { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
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+ { 0x380f, CRL_REG_LEN_08BIT, 0x40 },
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+ { 0x3810, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3813, CRL_REG_LEN_08BIT, 0x04 },
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+ { 0x381c, CRL_REG_LEN_08BIT, 0x08 },
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+ { 0x3820, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3822, CRL_REG_LEN_08BIT, 0x14 },
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+ { 0x3832, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3833, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x3834, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x383d, CRL_REG_LEN_08BIT, 0x20 },
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+ { 0x384c, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x384d, CRL_REG_LEN_08BIT, 0x14 },
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+ { 0x384e, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x384f, CRL_REG_LEN_08BIT, 0x40 },
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+ { 0x3850, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x3851, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x3852, CRL_REG_LEN_08BIT, 0x01 },
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+ { 0x3853, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3854, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3855, CRL_REG_LEN_08BIT, 0x05 },
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+ { 0x3856, CRL_REG_LEN_08BIT, 0x05 },
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+ { 0x3857, CRL_REG_LEN_08BIT, 0x33 },
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+ { 0x3858, CRL_REG_LEN_08BIT, 0x7c },
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+ { 0x3859, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x385a, CRL_REG_LEN_08BIT, 0x03 },
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+ { 0x385b, CRL_REG_LEN_08BIT, 0x05 },
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+ { 0x385c, CRL_REG_LEN_08BIT, 0x32 },
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+ { 0x385f, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3860, CRL_REG_LEN_08BIT, 0x10 },
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+ { 0x3861, CRL_REG_LEN_08BIT, 0x00 },
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+ { 0x3862, CRL_REG_LEN_08BIT, 0x40 },
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+ { 0x3863, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3864, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3865, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3866, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3b40, CRL_REG_LEN_08BIT, 0x3e },
|
|
+ { 0x3b41, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b42, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x3b43, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b44, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b45, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x3b46, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b47, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x3b84, CRL_REG_LEN_08BIT, 0x36 },
|
|
+ { 0x3b85, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b86, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b87, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x3b88, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b89, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x3b8a, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b8b, CRL_REG_LEN_08BIT, 0x0a },
|
|
+ { 0x3b8e, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x3b8f, CRL_REG_LEN_08BIT, 0xe8 },
|
|
+ { 0x3d85, CRL_REG_LEN_08BIT, 0x0b },
|
|
+ { 0x3d8c, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d8d, CRL_REG_LEN_08BIT, 0x26 },
|
|
+ { 0x3d97, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d98, CRL_REG_LEN_08BIT, 0x24 },
|
|
+ { 0x3d99, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d9a, CRL_REG_LEN_08BIT, 0x6d },
|
|
+ { 0x3d9b, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d9c, CRL_REG_LEN_08BIT, 0x6e },
|
|
+ { 0x3d9d, CRL_REG_LEN_08BIT, 0x73 },
|
|
+ { 0x3d9e, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x3e07, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3f00, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x4000, CRL_REG_LEN_08BIT, 0xf8 },
|
|
+ { 0x4001, CRL_REG_LEN_08BIT, 0xeb },
|
|
+ { 0x4004, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4005, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4008, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x4009, CRL_REG_LEN_08BIT, 0x0d },
|
|
+ { 0x400a, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x400b, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x400f, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x4010, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x4011, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x4016, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4017, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x4018, CRL_REG_LEN_08BIT, 0x18 },
|
|
+ { 0x401a, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x4028, CRL_REG_LEN_08BIT, 0x4f },
|
|
+ { 0x402e, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x402f, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4030, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4031, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4032, CRL_REG_LEN_08BIT, 0x9e },
|
|
+ { 0x4033, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x4308, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4501, CRL_REG_LEN_08BIT, 0x18 },
|
|
+ { 0x4502, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4507, CRL_REG_LEN_08BIT, 0x07 },
|
|
+ { 0x4580, CRL_REG_LEN_08BIT, 0xf8 },
|
|
+ { 0x4581, CRL_REG_LEN_08BIT, 0xc7 },
|
|
+ { 0x4582, CRL_REG_LEN_08BIT, 0x07 },
|
|
+ { 0x4602, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4603, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x460a, CRL_REG_LEN_08BIT, 0x36 },
|
|
+ { 0x460c, CRL_REG_LEN_08BIT, 0x60 },
|
|
+ { 0x4700, CRL_REG_LEN_08BIT, 0x2a },
|
|
+ { 0x470a, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x470b, CRL_REG_LEN_08BIT, 0x88 },
|
|
+ { 0x4800, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x480e, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x4813, CRL_REG_LEN_08BIT, 0xd2 },
|
|
+ { 0x4815, CRL_REG_LEN_08BIT, 0x2b },
|
|
+ { 0x4837, CRL_REG_LEN_08BIT, 0x28 },
|
|
+ { 0x484a, CRL_REG_LEN_08BIT, 0x3f },
|
|
+ { 0x484b, CRL_REG_LEN_08BIT, 0x67 },
|
|
+ { 0x4850, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4861, CRL_REG_LEN_08BIT, 0xa0 },
|
|
+ { 0x4886, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4900, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x4903, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x4f00, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x4f01, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x4f05, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x5180, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5181, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5182, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5183, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5184, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5185, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5186, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5187, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a0, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a1, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a6, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c0, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c1, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c6, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5380, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5381, CRL_REG_LEN_08BIT, 0x94 },
|
|
+ { 0x5382, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x53a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x53a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x53a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x53a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x53a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x53a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5400, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5401, CRL_REG_LEN_08BIT, 0x94 },
|
|
+ { 0x5402, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x5420, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x5422, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5423, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5424, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5425, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5427, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5480, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5481, CRL_REG_LEN_08BIT, 0x94 },
|
|
+ { 0x5482, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x54a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x54a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x54a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x54a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x54a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x54a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5800, CRL_REG_LEN_08BIT, 0x31 },
|
|
+ { 0x5801, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5804, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5805, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x5806, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x5807, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x580e, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x5812, CRL_REG_LEN_08BIT, 0x34 },
|
|
+ { 0x5000, CRL_REG_LEN_08BIT, 0x89 },
|
|
+ { 0x5001, CRL_REG_LEN_08BIT, 0x42 },
|
|
+ { 0x5002, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5003, CRL_REG_LEN_08BIT, 0x16 },
|
|
+ { 0x503e, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x503f, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5602, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5603, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5604, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5605, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5606, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5607, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5608, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5609, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x560a, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x560b, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x560c, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x560d, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x560e, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x560f, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5610, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5611, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5612, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5613, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5614, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5615, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5616, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5617, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5618, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5619, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5642, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5643, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5644, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5645, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5646, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5647, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5648, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5649, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x564a, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x564b, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x564c, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x564d, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x564e, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x564f, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5650, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5651, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5652, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5653, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5654, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5655, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5656, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5657, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5658, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5659, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5682, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5683, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5684, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5685, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5686, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5687, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5688, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5689, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x568a, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x568b, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x568c, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x568d, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x568e, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x568f, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5690, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5691, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5692, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5693, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5694, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5695, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5696, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5697, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5698, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5699, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5709, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x5749, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x5789, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x5200, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x5201, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x5202, CRL_REG_LEN_08BIT, 0x73 },
|
|
+ { 0x5203, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x5205, CRL_REG_LEN_08BIT, 0x6c },
|
|
+ { 0x5285, CRL_REG_LEN_08BIT, 0x6c },
|
|
+ { 0x5305, CRL_REG_LEN_08BIT, 0x6c },
|
|
+ { 0x5082, CRL_REG_LEN_08BIT, 0xb0 },
|
|
+ { 0x50c2, CRL_REG_LEN_08BIT, 0xb0 },
|
|
+ { 0x5102, CRL_REG_LEN_08BIT, 0xb0 },
|
|
+ { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x380f, CRL_REG_LEN_08BIT, 0x34 },
|
|
+ { 0x380c, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x380d, CRL_REG_LEN_08BIT, 0x78 },
|
|
+ { 0x384c, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x384d, CRL_REG_LEN_08BIT, 0x14 },
|
|
+ { 0x460a, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x0100, CRL_REG_LEN_08BIT, 0x01 },
|
|
+};
|
|
+
|
|
+static struct crl_register_write_rep ox03a10_1920_1088_12DCG_12VS[] = {
|
|
+ { 0x4d09, CRL_REG_LEN_08BIT, 0x5f },
|
|
+ { 0x0104, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x0303, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x0305, CRL_REG_LEN_08BIT, 0x36 },
|
|
+ { 0x0307, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x0316, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x0317, CRL_REG_LEN_08BIT, 0x12 },
|
|
+ { 0x0323, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x0325, CRL_REG_LEN_08BIT, 0x6c },
|
|
+ { 0x0326, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x032b, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x0400, CRL_REG_LEN_08BIT, 0xe7 },
|
|
+ { 0x0401, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x0404, CRL_REG_LEN_08BIT, 0x2b },
|
|
+ { 0x0405, CRL_REG_LEN_08BIT, 0x32 },
|
|
+ { 0x0406, CRL_REG_LEN_08BIT, 0x33 },
|
|
+ { 0x0407, CRL_REG_LEN_08BIT, 0x8f },
|
|
+ { 0x0408, CRL_REG_LEN_08BIT, 0x0c },
|
|
+ { 0x0410, CRL_REG_LEN_08BIT, 0xe7 },
|
|
+ { 0x0411, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x0414, CRL_REG_LEN_08BIT, 0x2b },
|
|
+ { 0x0415, CRL_REG_LEN_08BIT, 0x32 },
|
|
+ { 0x0416, CRL_REG_LEN_08BIT, 0x33 },
|
|
+ { 0x0417, CRL_REG_LEN_08BIT, 0x8f },
|
|
+ { 0x0418, CRL_REG_LEN_08BIT, 0x0c },
|
|
+ { 0x3002, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x3012, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x3016, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x3017, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x3018, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x3019, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x301a, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x301b, CRL_REG_LEN_08BIT, 0xb4 },
|
|
+ { 0x301e, CRL_REG_LEN_08BIT, 0xb8 },
|
|
+ { 0x301f, CRL_REG_LEN_08BIT, 0xe1 },
|
|
+ { 0x3022, CRL_REG_LEN_08BIT, 0xf8 },
|
|
+ { 0x3023, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x3024, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x3028, CRL_REG_LEN_08BIT, 0xf0 },
|
|
+ { 0x3029, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x3706, CRL_REG_LEN_08BIT, 0x39 },
|
|
+ { 0x370a, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x370b, CRL_REG_LEN_08BIT, 0xa3 },
|
|
+ { 0x3712, CRL_REG_LEN_08BIT, 0x12 },
|
|
+ { 0x3713, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3716, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x371d, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x3721, CRL_REG_LEN_08BIT, 0x1c },
|
|
+ { 0x372c, CRL_REG_LEN_08BIT, 0x17 },
|
|
+ { 0x3733, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x3741, CRL_REG_LEN_08BIT, 0x44 },
|
|
+ { 0x3742, CRL_REG_LEN_08BIT, 0x34 },
|
|
+ { 0x3746, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x374b, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x3755, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x376c, CRL_REG_LEN_08BIT, 0x15 },
|
|
+ { 0x376d, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x376f, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x3770, CRL_REG_LEN_08BIT, 0x91 },
|
|
+ { 0x3771, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x3774, CRL_REG_LEN_08BIT, 0x82 },
|
|
+ { 0x3777, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3779, CRL_REG_LEN_08BIT, 0x22 },
|
|
+ { 0x377a, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x377b, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x377c, CRL_REG_LEN_08BIT, 0x48 },
|
|
+ { 0x3785, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x3790, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x3793, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x379c, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x37a1, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x37b3, CRL_REG_LEN_08BIT, 0x0a },
|
|
+ { 0x37bb, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x37be, CRL_REG_LEN_08BIT, 0xe0 },
|
|
+ { 0x37bf, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x37c6, CRL_REG_LEN_08BIT, 0x48 },
|
|
+ { 0x37c7, CRL_REG_LEN_08BIT, 0x38 },
|
|
+ { 0x37c9, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x37ca, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x37cb, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x37cc, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x37d1, CRL_REG_LEN_08BIT, 0x39 },
|
|
+ { 0x37d2, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x37d3, CRL_REG_LEN_08BIT, 0xa3 },
|
|
+ { 0x37d5, CRL_REG_LEN_08BIT, 0x39 },
|
|
+ { 0x37d6, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x37d7, CRL_REG_LEN_08BIT, 0xa3 },
|
|
+ { 0x3c06, CRL_REG_LEN_08BIT, 0x29 },
|
|
+ { 0x3c0b, CRL_REG_LEN_08BIT, 0xa8 },
|
|
+ { 0x3c12, CRL_REG_LEN_08BIT, 0x89 },
|
|
+ { 0x3c14, CRL_REG_LEN_08BIT, 0x81 },
|
|
+ { 0x3c18, CRL_REG_LEN_08BIT, 0x0c },
|
|
+ { 0x3c3b, CRL_REG_LEN_08BIT, 0x38 },
|
|
+ { 0x3c53, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x3c55, CRL_REG_LEN_08BIT, 0xeb },
|
|
+ { 0x3101, CRL_REG_LEN_08BIT, 0x32 },
|
|
+ { 0x3192, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3193, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3206, CRL_REG_LEN_08BIT, 0xc8 },
|
|
+ { 0x3216, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x3304, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x3400, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x3409, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x3600, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3601, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3602, CRL_REG_LEN_08BIT, 0x42 },
|
|
+ { 0x3603, CRL_REG_LEN_08BIT, 0xe3 },
|
|
+ { 0x3604, CRL_REG_LEN_08BIT, 0x93 },
|
|
+ { 0x3605, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x3606, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x3607, CRL_REG_LEN_08BIT, 0x4a },
|
|
+ { 0x3608, CRL_REG_LEN_08BIT, 0x98 },
|
|
+ { 0x3609, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x360a, CRL_REG_LEN_08BIT, 0xd0 },
|
|
+ { 0x360b, CRL_REG_LEN_08BIT, 0x0b },
|
|
+ { 0x360e, CRL_REG_LEN_08BIT, 0x88 },
|
|
+ { 0x3610, CRL_REG_LEN_08BIT, 0x89 },
|
|
+ { 0x3611, CRL_REG_LEN_08BIT, 0x4b },
|
|
+ { 0x3612, CRL_REG_LEN_08BIT, 0x4e },
|
|
+ { 0x3619, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3620, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x3621, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x3626, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x362c, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x362d, CRL_REG_LEN_08BIT, 0x12 },
|
|
+ { 0x362e, CRL_REG_LEN_08BIT, 0x0a },
|
|
+ { 0x362f, CRL_REG_LEN_08BIT, 0x17 },
|
|
+ { 0x3630, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x3631, CRL_REG_LEN_08BIT, 0x3f },
|
|
+ { 0x3632, CRL_REG_LEN_08BIT, 0x99 },
|
|
+ { 0x3633, CRL_REG_LEN_08BIT, 0x99 },
|
|
+ { 0x3643, CRL_REG_LEN_08BIT, 0x0c },
|
|
+ { 0x3644, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3645, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x3646, CRL_REG_LEN_08BIT, 0x0f },
|
|
+ { 0x3647, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x3648, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3649, CRL_REG_LEN_08BIT, 0x11 },
|
|
+ { 0x364a, CRL_REG_LEN_08BIT, 0x12 },
|
|
+ { 0x364c, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x364d, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x364e, CRL_REG_LEN_08BIT, 0x12 },
|
|
+ { 0x364f, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x3652, CRL_REG_LEN_08BIT, 0xc5 },
|
|
+ { 0x3654, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3656, CRL_REG_LEN_08BIT, 0xcf },
|
|
+ { 0x3657, CRL_REG_LEN_08BIT, 0x88 },
|
|
+ { 0x3658, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x365a, CRL_REG_LEN_08BIT, 0x3f },
|
|
+ { 0x365b, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x365c, CRL_REG_LEN_08BIT, 0x17 },
|
|
+ { 0x365d, CRL_REG_LEN_08BIT, 0x0a },
|
|
+ { 0x3660, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x3661, CRL_REG_LEN_08BIT, 0x07 },
|
|
+ { 0x3662, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3663, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x3665, CRL_REG_LEN_08BIT, 0x12 },
|
|
+ { 0x3666, CRL_REG_LEN_08BIT, 0x13 },
|
|
+ { 0x3667, CRL_REG_LEN_08BIT, 0x14 },
|
|
+ { 0x3668, CRL_REG_LEN_08BIT, 0x95 },
|
|
+ { 0x3669, CRL_REG_LEN_08BIT, 0x16 },
|
|
+ { 0x366f, CRL_REG_LEN_08BIT, 0xc4 },
|
|
+ { 0x3671, CRL_REG_LEN_08BIT, 0x37 },
|
|
+ { 0x3673, CRL_REG_LEN_08BIT, 0x6a },
|
|
+ { 0x3678, CRL_REG_LEN_08BIT, 0x88 },
|
|
+ { 0x3800, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3801, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3802, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3803, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x3804, CRL_REG_LEN_08BIT, 0x07 },
|
|
+ { 0x3805, CRL_REG_LEN_08BIT, 0x8f },
|
|
+ { 0x3806, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x3807, CRL_REG_LEN_08BIT, 0x0c },
|
|
+ { 0x3808, CRL_REG_LEN_08BIT, 0x07 },
|
|
+ { 0x3809, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x380a, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x380b, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x380f, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3810, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3813, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x381c, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x3820, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3822, CRL_REG_LEN_08BIT, 0x14 },
|
|
+ { 0x3832, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3833, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x3834, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x383d, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x384c, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x384d, CRL_REG_LEN_08BIT, 0x14 },
|
|
+ { 0x384e, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x384f, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3850, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x3851, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x3852, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x3853, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3854, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3855, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x3856, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x3857, CRL_REG_LEN_08BIT, 0x33 },
|
|
+ { 0x3858, CRL_REG_LEN_08BIT, 0x7c },
|
|
+ { 0x3859, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x385a, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x385b, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x385c, CRL_REG_LEN_08BIT, 0x32 },
|
|
+ { 0x385f, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3860, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x3861, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3862, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3863, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3864, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3865, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3866, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3b40, CRL_REG_LEN_08BIT, 0x3e },
|
|
+ { 0x3b41, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b42, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x3b43, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b44, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b45, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x3b46, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b47, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x3b84, CRL_REG_LEN_08BIT, 0x36 },
|
|
+ { 0x3b85, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b86, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b87, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x3b88, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b89, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x3b8a, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x3b8b, CRL_REG_LEN_08BIT, 0x0a },
|
|
+ { 0x3b8e, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x3b8f, CRL_REG_LEN_08BIT, 0xe8 },
|
|
+ { 0x3d85, CRL_REG_LEN_08BIT, 0x0b },
|
|
+ { 0x3d8c, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d8d, CRL_REG_LEN_08BIT, 0x26 },
|
|
+ { 0x3d97, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d98, CRL_REG_LEN_08BIT, 0x24 },
|
|
+ { 0x3d99, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d9a, CRL_REG_LEN_08BIT, 0x6d },
|
|
+ { 0x3d9b, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x3d9c, CRL_REG_LEN_08BIT, 0x6e },
|
|
+ { 0x3d9d, CRL_REG_LEN_08BIT, 0x73 },
|
|
+ { 0x3d9e, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x3e07, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x3f00, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x4000, CRL_REG_LEN_08BIT, 0xf8 },
|
|
+ { 0x4001, CRL_REG_LEN_08BIT, 0xeb },
|
|
+ { 0x4004, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4005, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4008, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x4009, CRL_REG_LEN_08BIT, 0x0d },
|
|
+ { 0x400a, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x400b, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x400f, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x4010, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x4011, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x4016, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4017, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x4018, CRL_REG_LEN_08BIT, 0x18 },
|
|
+ { 0x401a, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x4028, CRL_REG_LEN_08BIT, 0x4f },
|
|
+ { 0x402e, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x402f, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4030, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4031, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4032, CRL_REG_LEN_08BIT, 0x9e },
|
|
+ { 0x4033, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x4308, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4501, CRL_REG_LEN_08BIT, 0x18 },
|
|
+ { 0x4502, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4507, CRL_REG_LEN_08BIT, 0x07 },
|
|
+ { 0x4580, CRL_REG_LEN_08BIT, 0xf8 },
|
|
+ { 0x4581, CRL_REG_LEN_08BIT, 0xc7 },
|
|
+ { 0x4582, CRL_REG_LEN_08BIT, 0x07 },
|
|
+ { 0x4602, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4603, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x460a, CRL_REG_LEN_08BIT, 0x36 },
|
|
+ { 0x460c, CRL_REG_LEN_08BIT, 0x60 },
|
|
+ { 0x4700, CRL_REG_LEN_08BIT, 0x2a },
|
|
+ { 0x470a, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x470b, CRL_REG_LEN_08BIT, 0x88 },
|
|
+ { 0x4800, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x480e, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x4813, CRL_REG_LEN_08BIT, 0xd2 },
|
|
+ { 0x4815, CRL_REG_LEN_08BIT, 0x2b },
|
|
+ { 0x4837, CRL_REG_LEN_08BIT, 0x18 },
|
|
+ { 0x484a, CRL_REG_LEN_08BIT, 0x3f },
|
|
+ { 0x484b, CRL_REG_LEN_08BIT, 0x67 },
|
|
+ { 0x4850, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x4861, CRL_REG_LEN_08BIT, 0xa0 },
|
|
+ { 0x4886, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x4900, CRL_REG_LEN_08BIT, 0x08 },
|
|
+ { 0x4903, CRL_REG_LEN_08BIT, 0x80 },
|
|
+ { 0x4f00, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x4f01, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x4f05, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x5180, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5181, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5182, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5183, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5184, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5185, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5186, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5187, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a0, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a1, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51a6, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c0, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c1, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x51c6, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x51c7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5380, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5381, CRL_REG_LEN_08BIT, 0x94 },
|
|
+ { 0x5382, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x53a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x53a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x53a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x53a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x53a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x53a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5400, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5401, CRL_REG_LEN_08BIT, 0x94 },
|
|
+ { 0x5402, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x5420, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x5422, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5423, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5424, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x5425, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5427, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5480, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5481, CRL_REG_LEN_08BIT, 0x94 },
|
|
+ { 0x5482, CRL_REG_LEN_08BIT, 0x2e },
|
|
+ { 0x54a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
+ { 0x54a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x54a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x54a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
+ { 0x54a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x54a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5800, CRL_REG_LEN_08BIT, 0x31 },
|
|
+ { 0x5801, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5804, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5805, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x5806, CRL_REG_LEN_08BIT, 0x01 },
|
|
+ { 0x5807, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x580e, CRL_REG_LEN_08BIT, 0x10 },
|
|
+ { 0x5812, CRL_REG_LEN_08BIT, 0x34 },
|
|
+ { 0x5000, CRL_REG_LEN_08BIT, 0x89 },
|
|
+ { 0x5001, CRL_REG_LEN_08BIT, 0x42 },
|
|
+ { 0x5002, CRL_REG_LEN_08BIT, 0x19 },
|
|
+ { 0x5003, CRL_REG_LEN_08BIT, 0x16 },
|
|
+ { 0x503e, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x503f, CRL_REG_LEN_08BIT, 0x00 },
|
|
+ { 0x5602, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5603, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5604, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5605, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5606, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5607, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5608, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5609, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x560a, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x560b, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x560c, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x560d, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x560e, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x560f, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5610, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5611, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5612, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5613, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5614, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5615, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5616, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5617, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5618, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5619, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5642, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5643, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5644, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5645, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5646, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5647, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5648, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5649, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x564a, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x564b, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x564c, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x564d, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x564e, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x564f, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5650, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5651, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5652, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5653, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5654, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5655, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5656, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5657, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5658, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5659, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5682, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5683, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5684, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5685, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5686, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5687, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5688, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5689, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x568a, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x568b, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x568c, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x568d, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x568e, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x568f, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5690, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5691, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5692, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5693, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5694, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5695, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5696, CRL_REG_LEN_08BIT, 0x02 },
|
|
+ { 0x5697, CRL_REG_LEN_08BIT, 0x58 },
|
|
+ { 0x5698, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x5699, CRL_REG_LEN_08BIT, 0x20 },
|
|
+ { 0x5709, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x5749, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x5789, CRL_REG_LEN_08BIT, 0x0e },
|
|
+ { 0x5200, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x5201, CRL_REG_LEN_08BIT, 0x70 },
|
|
+ { 0x5202, CRL_REG_LEN_08BIT, 0x73 },
|
|
+ { 0x5203, CRL_REG_LEN_08BIT, 0xff },
|
|
+ { 0x5205, CRL_REG_LEN_08BIT, 0x6c },
|
|
+ { 0x5285, CRL_REG_LEN_08BIT, 0x6c },
|
|
+ { 0x5305, CRL_REG_LEN_08BIT, 0x6c },
|
|
+ { 0x5082, CRL_REG_LEN_08BIT, 0xb0 },
|
|
+ { 0x50c2, CRL_REG_LEN_08BIT, 0xb0 },
|
|
+ { 0x5102, CRL_REG_LEN_08BIT, 0xb0 },
|
|
+ { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
|
|
+ { 0x380f, CRL_REG_LEN_08BIT, 0x34 },
|
|
+ { 0x380c, CRL_REG_LEN_08BIT, 0x06 },
|
|
+ { 0x380d, CRL_REG_LEN_08BIT, 0xcc },
|
|
+ { 0x384c, CRL_REG_LEN_08BIT, 0x03 },
|
|
+ { 0x384d, CRL_REG_LEN_08BIT, 0xc0 },
|
|
+ { 0x460c, CRL_REG_LEN_08BIT, 0x40 },
|
|
+ { 0x0100, CRL_REG_LEN_08BIT, 0x01 },
|
|
+};
|
|
+
|
|
+struct crl_ctrl_data_pair ox03a10_ctrl_data_modes[] = {
|
|
+ {
|
|
+ .ctrl_id = CRL_CID_EXPOSURE_MODE,
|
|
+ .data = 0,
|
|
+ },
|
|
+ {
|
|
+ .ctrl_id = CRL_CID_EXPOSURE_MODE,
|
|
+ .data = 1,
|
|
+ },
|
|
+ {
|
|
+ .ctrl_id = CRL_CID_EXPOSURE_MODE,
|
|
+ .data = 2,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops bits_5_0[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_AND,
|
|
+ .operand.entity_val = 0x3F,
|
|
+ },
|
|
+ {
|
|
+ .op = CRL_BITWISE_LSHIFT,
|
|
+ .operand.entity_val = 2,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops bits_10_6[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_RSHIFT,
|
|
+ .operand.entity_val = 6,
|
|
+ },
|
|
+ {
|
|
+ .op = CRL_BITWISE_AND,
|
|
+ .operand.entity_val = 0x1F,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops bits_13_10[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_RSHIFT,
|
|
+ .operand.entity_val = 10,
|
|
+ },
|
|
+ {
|
|
+ .op = CRL_BITWISE_AND,
|
|
+ .operand.entity_val = 0xF,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops bits_9_2[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_RSHIFT,
|
|
+ .operand.entity_val = 2,
|
|
+ },
|
|
+ {
|
|
+ .op = CRL_BITWISE_AND,
|
|
+ .operand.entity_val = 0xFF,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops bits_1_0[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_AND,
|
|
+ .operand.entity_val = 0x3,
|
|
+ },
|
|
+ {
|
|
+ .op = CRL_BITWISE_LSHIFT,
|
|
+ .operand.entity_val = 6,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops bits_15_8[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_RSHIFT,
|
|
+ .operand.entity_val = 8,
|
|
+ },
|
|
+ {
|
|
+ .op = CRL_BITWISE_AND,
|
|
+ .operand.entity_val = 0xff,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops bits_7_0[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_AND,
|
|
+ .operand.entity_val = 0xff,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_hcg_real_gain[] = {
|
|
+ {
|
|
+ .address = 0x3508,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_10_6),
|
|
+ .ops = bits_10_6,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x3509,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_5_0),
|
|
+ .ops = bits_5_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_hcg_digital_gain[] = {
|
|
+ {
|
|
+ .address = 0x350a,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_13_10),
|
|
+ .ops = bits_13_10,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x350b,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_9_2),
|
|
+ .ops = bits_9_2,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x350c,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_1_0),
|
|
+ .ops = bits_1_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_lcg_real_gain[] = {
|
|
+ {
|
|
+ .address = 0x3548,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_10_6),
|
|
+ .ops = bits_10_6,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x3549,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_5_0),
|
|
+ .ops = bits_5_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_lcg_digital_gain[] = {
|
|
+ {
|
|
+ .address = 0x354a,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_13_10),
|
|
+ .ops = bits_13_10,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x354b,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_9_2),
|
|
+ .ops = bits_9_2,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x354c,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_1_0),
|
|
+ .ops = bits_1_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_dcg_exposure_coarse[] = {
|
|
+ {
|
|
+ .address = 0x3501,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_15_8),
|
|
+ .ops = bits_15_8,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x3502,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_7_0),
|
|
+ .ops = bits_7_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_vs_real_gain[] = {
|
|
+ {
|
|
+ .address = 0x3588,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_10_6),
|
|
+ .ops = bits_10_6,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x3589,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_5_0),
|
|
+ .ops = bits_5_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_vs_digital_gain[] = {
|
|
+ {
|
|
+ .address = 0x358a,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_13_10),
|
|
+ .ops = bits_13_10,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x358b,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_9_2),
|
|
+ .ops = bits_9_2,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x358c,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_1_0),
|
|
+ .ops = bits_1_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_vs_exposure_coarse[] = {
|
|
+ {
|
|
+ .address = 0x3581,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_15_8),
|
|
+ .ops = bits_15_8,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x3582,
|
|
+ .len = CRL_REG_LEN_08BIT,
|
|
+ .ops_items = ARRAY_SIZE(bits_7_0),
|
|
+ .ops = bits_7_0,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops ox03a10_mirror_ops[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_LSHIFT,
|
|
+ .operand.entity_val = 2,
|
|
+ },
|
|
+ {
|
|
+ .op = CRL_BITWISE_OR,
|
|
+ .operand.entity_val = 0x20,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ox03a10_h_flip_regs[] = {
|
|
+ {
|
|
+ .address = 0x3821,
|
|
+ .len = CRL_REG_LEN_08BIT | CRL_REG_READ_AND_UPDATE,
|
|
+ .ops_items = ARRAY_SIZE(ox03a10_mirror_ops),
|
|
+ .ops = ox03a10_mirror_ops,
|
|
+ .mask = 0x24,
|
|
+ },
|
|
+ {
|
|
+ .address = 0x3811,
|
|
+ .len = CRL_REG_LEN_08BIT | CRL_REG_READ_AND_UPDATE,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0x1,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* keep GRBG no change during flip, for tuning file handle GRBG only */
|
|
+static struct crl_flip_data ox03a10_flip_configurations[] = {
|
|
+ {
|
|
+ .flip = CRL_FLIP_DEFAULT_NONE,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
+ },
|
|
+ {
|
|
+ .flip = CRL_FLIP_HFLIP,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
+ },
|
|
+};
|
|
+
|
|
+struct crl_v4l2_ctrl ox03a10_v4l2_ctrls[] = {
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "DCG exposure",
|
|
+ .ctrl_id = V4L2_CID_EXPOSURE,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 1,
|
|
+ .data.std_data.max = 1280,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x40,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_dcg_exposure_coarse),
|
|
+ .regs = ox03a10_dcg_exposure_coarse,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "VS exposure",
|
|
+ .ctrl_id = CRL_CID_EXPOSURE_SHS1,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 1,
|
|
+ .data.std_data.max = 1280,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x40,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_vs_exposure_coarse),
|
|
+ .regs = ox03a10_vs_exposure_coarse,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "HCG digital gain",
|
|
+ .ctrl_id = V4L2_CID_GAIN,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x400,
|
|
+ .data.std_data.max = 0x3FFF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x400,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_hcg_digital_gain),
|
|
+ .regs = ox03a10_hcg_digital_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "HCG analog gain",
|
|
+ .ctrl_id = V4L2_CID_ANALOGUE_GAIN,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x40,
|
|
+ .data.std_data.max = 0x400,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x40,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_hcg_real_gain),
|
|
+ .regs = ox03a10_hcg_real_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "HCG digital gain",
|
|
+ .ctrl_id = V4L2_CID_DIGITAL_GAIN,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x400,
|
|
+ .data.std_data.max = 0x3FFF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x400,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_hcg_digital_gain),
|
|
+ .regs = ox03a10_hcg_digital_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "LCG analog gain",
|
|
+ .ctrl_id = CRL_CID_ANALOG_GAIN_S,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x40,
|
|
+ .data.std_data.max = 0x400,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x40,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_lcg_real_gain),
|
|
+ .regs = ox03a10_lcg_real_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "LCG digital gain",
|
|
+ .ctrl_id = CRL_CID_DIGITAL_GAIN_S,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x400,
|
|
+ .data.std_data.max = 0x3FFF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x400,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_lcg_digital_gain),
|
|
+ .regs = ox03a10_lcg_digital_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "LCG analog gain",
|
|
+ .ctrl_id = CRL_CID_ANALOG_GAIN_L,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x40,
|
|
+ .data.std_data.max = 0x400,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x40,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_lcg_real_gain),
|
|
+ .regs = ox03a10_lcg_real_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "LCG digital gain",
|
|
+ .ctrl_id = CRL_CID_DIGITAL_GAIN_L,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x400,
|
|
+ .data.std_data.max = 0x3FFF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x400,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_lcg_digital_gain),
|
|
+ .regs = ox03a10_lcg_digital_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "VS analog gain",
|
|
+ .ctrl_id = CRL_CID_ANALOG_GAIN_VS,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x40,
|
|
+ .data.std_data.max = 0x400,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x40,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_vs_real_gain),
|
|
+ .regs = ox03a10_vs_real_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "VS digital gain",
|
|
+ .ctrl_id = CRL_CID_DIGITAL_GAIN_VS,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x400,
|
|
+ .data.std_data.max = 0x3FFF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x400,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_vs_digital_gain),
|
|
+ .regs = ox03a10_vs_digital_gain,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .name = "CRL_CID_EXPOSURE_MODE",
|
|
+ .ctrl_id = CRL_CID_EXPOSURE_MODE,
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = 1,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_MODE_SELECTION,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_GET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = V4L2_CID_PIXEL_RATE,
|
|
+ .name = "V4L2_CID_PIXEL_RATE_PA",
|
|
+ .type = CRL_V4L2_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = INT_MAX,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = V4L2_CID_LINE_LENGTH_PIXELS,
|
|
+ .name = "Line Length Pixels",
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 1920,
|
|
+ .data.std_data.max = 65535,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 2700,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .ctrl = 0,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_llp_regs),
|
|
+ .regs = ar0231at_llp_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = V4L2_CID_FRAME_LENGTH_LINES,
|
|
+ .name = "Frame Length Lines",
|
|
+ .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 1088,
|
|
+ .data.std_data.max = 65535,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 1480,
|
|
+ .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .ctrl = 0,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_fll_regs),
|
|
+ .regs = ar0231at_fll_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = V4L2_CID_HFLIP,
|
|
+ .name = "V4L2_CID_HFLIP",
|
|
+ .type = CRL_V4L2_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = 1,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 1,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .ctrl = 0,
|
|
+ .regs_items = ARRAY_SIZE(ox03a10_h_flip_regs),
|
|
+ .regs = ox03a10_h_flip_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_BINNER,
|
|
+ .op_type = CRL_V4L2_CTRL_GET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = V4L2_CID_PIXEL_RATE,
|
|
+ .name = "V4L2_CID_PIXEL_RATE_CSI",
|
|
+ .type = CRL_V4L2_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = INT_MAX,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_BINNER,
|
|
+ .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
+ .context = SENSOR_IDLE,
|
|
+ .ctrl_id = V4L2_CID_LINK_FREQ,
|
|
+ .name = "V4L2_CID_LINK_FREQ",
|
|
+ .type = CRL_V4L2_CTRL_TYPE_MENU_INT,
|
|
+ .data.v4l2_int_menu.def = 0,
|
|
+ .data.v4l2_int_menu.max = 0,
|
|
+ .data.v4l2_int_menu.menu = 0,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+};
|
|
+
|
|
+struct crl_csi_data_fmt ox03a10_crl_csi_data_fmt[] = {
|
|
+ {
|
|
+ .code = MEDIA_BUS_FMT_SGRBG12_1X12,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
+ .bits_per_pixel = 12,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+};
|
|
+
|
|
+struct crl_pll_configuration ox03a10_pll_configurations[] = {
|
|
+ {
|
|
+ .input_clk = 27000000,
|
|
+ .op_sys_clk = 108000000,
|
|
+ .bitsperpixel = 12,
|
|
+ .pixel_rate_csi = 108000000,
|
|
+ .pixel_rate_pa = 108000000,
|
|
+ // pixel_rate = op_sys_clk*2 *csi_lanes/bitsperpixel
|
|
+ .csi_lanes = 4,
|
|
+ .comp_items = 0,
|
|
+ .ctrl_data = 0,
|
|
+ .pll_regs_items = 0,
|
|
+ .pll_regs = 0,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct crl_register_write_rep ox03a10_streamoff_regs[] = {
|
|
+ { 0x0100, CRL_REG_LEN_08BIT, 0x00 }
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops ox03a10_frame_desc_width_ops[] = {
|
|
+ {
|
|
+ .op = CRL_ASSIGNMENT,
|
|
+ .operand.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_VAR_REF,
|
|
+ .operand.entity_val = CRL_VAR_REF_OUTPUT_WIDTH,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops ox03a10_frame_desc_height_ops[] = {
|
|
+ {
|
|
+ .op = CRL_ASSIGNMENT,
|
|
+ .operand.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_CONST,
|
|
+ .operand.entity_val = 1,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct crl_frame_desc ox03a10_frame_desc[] = {
|
|
+ {
|
|
+ .flags.entity_val = 0,
|
|
+ .bpp.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_VAR_REF,
|
|
+ .bpp.entity_val = CRL_VAR_REF_BITSPERPIXEL,
|
|
+ .pixelcode.entity_val = MEDIA_BUS_FMT_FIXED,
|
|
+ .length.entity_val = 0,
|
|
+ .start_line.entity_val = 0,
|
|
+ .start_pixel.entity_val = 0,
|
|
+ .width = {
|
|
+ .ops_items = ARRAY_SIZE(ox03a10_frame_desc_width_ops),
|
|
+ .ops = ox03a10_frame_desc_width_ops,
|
|
+ },
|
|
+ .height = {
|
|
+ .ops_items = ARRAY_SIZE(ox03a10_frame_desc_height_ops),
|
|
+ .ops = ox03a10_frame_desc_height_ops,
|
|
+ },
|
|
+ .csi2_channel.entity_val = 0,
|
|
+ .csi2_data_type.entity_val = 0x12,
|
|
+ },
|
|
+ {
|
|
+ .flags.entity_val = 0,
|
|
+ .bpp.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_VAR_REF,
|
|
+ .bpp.entity_val = CRL_VAR_REF_BITSPERPIXEL,
|
|
+ .pixelcode.entity_val = MEDIA_BUS_FMT_FIXED,
|
|
+ .length.entity_val = 0,
|
|
+ .start_line.entity_val = 0,
|
|
+ .start_pixel.entity_val = 0,
|
|
+ .width = {
|
|
+ .ops_items = ARRAY_SIZE(ox03a10_frame_desc_width_ops),
|
|
+ .ops = ox03a10_frame_desc_width_ops,
|
|
+ },
|
|
+ .height = {
|
|
+ .ops_items = ARRAY_SIZE(ox03a10_frame_desc_height_ops),
|
|
+ .ops = ox03a10_frame_desc_height_ops,
|
|
+ },
|
|
+ .csi2_channel.entity_val = 1,
|
|
+ .csi2_data_type.entity_val = 0x12,
|
|
+ },
|
|
+};
|
|
+
|
|
+struct crl_sensor_limits ox03a10_sensor_limits = {
|
|
+ .x_addr_min = 0,
|
|
+ .y_addr_min = 0,
|
|
+ .x_addr_max = 1920,
|
|
+ .y_addr_max = 1088,
|
|
+};
|
|
+
|
|
+struct crl_mode_rep ox03a10_modes[] = {
|
|
+ {
|
|
+ .sd_rects_items = ARRAY_SIZE(ox03a10_1920_1088_rects),
|
|
+ .sd_rects = ox03a10_1920_1088_rects,
|
|
+ .binn_hor = 1,
|
|
+ .binn_vert = 1,
|
|
+ .scale_m = 1,
|
|
+ .width = 1920,
|
|
+ .height = 1088,
|
|
+ .comp_items = 1,
|
|
+ .ctrl_data = &ox03a10_ctrl_data_modes[0],
|
|
+ .mode_regs_items = ARRAY_SIZE(ox03a10_1920_1088_12DCG),
|
|
+ .mode_regs = ox03a10_1920_1088_12DCG,
|
|
+ },
|
|
+ {
|
|
+ .sd_rects_items = ARRAY_SIZE(ox03a10_1920_1088_rects),
|
|
+ .sd_rects = ox03a10_1920_1088_rects,
|
|
+ .binn_hor = 1,
|
|
+ .binn_vert = 1,
|
|
+ .scale_m = 1,
|
|
+ .width = 1920,
|
|
+ .height = 1088,
|
|
+ .comp_items = 1,
|
|
+ .ctrl_data = &ox03a10_ctrl_data_modes[1],
|
|
+ .mode_regs_items = ARRAY_SIZE(ox03a10_1920_1088_12DCG_12VS),
|
|
+ .mode_regs = ox03a10_1920_1088_12DCG_12VS,
|
|
+ },
|
|
+};
|
|
+
|
|
+#endif /* __CRLMODULE_OX03A10_COMMON_H_ */
|
|
diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h b/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h
|
|
index 2a28c075cda2..cb2c89cbfb9b 100644
|
|
--- a/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h
|
|
+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_configuration.h
|
|
@@ -9,21 +9,7 @@
|
|
#define __CRLMODULE_OX03A10_CONFIGURATION_H_
|
|
|
|
#include "crlmodule-sensor-ds.h"
|
|
-
|
|
-struct crl_sensor_detect_config ox03a10_sensor_detect_regset[] = {
|
|
- {
|
|
- .reg = {0x300A, CRL_REG_LEN_08BIT, 0x58},
|
|
- .width = 12,
|
|
- },
|
|
- {
|
|
- .reg = {0x300B, CRL_REG_LEN_08BIT, 0x03},
|
|
- .width = 12,
|
|
- },
|
|
- {
|
|
- .reg = {0x300C, CRL_REG_LEN_08BIT, 0x41},
|
|
- .width = 12,
|
|
- }
|
|
-};
|
|
+#include "crl_ox03a10_common.h"
|
|
|
|
struct crl_sensor_subdev_config ox03a10_sensor_subdevs[] = {
|
|
{
|
|
@@ -36,1644 +22,6 @@ struct crl_sensor_subdev_config ox03a10_sensor_subdevs[] = {
|
|
}
|
|
};
|
|
|
|
-struct crl_sensor_limits ox03a10_sensor_limits = {
|
|
- .x_addr_min = 0,
|
|
- .y_addr_min = 0,
|
|
- .x_addr_max = 1920,
|
|
- .y_addr_max = 1088,
|
|
-};
|
|
-
|
|
-struct crl_subdev_rect_rep ox03a10_1920_1088_rects[] = {
|
|
- {
|
|
- .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .in_rect.left = 0,
|
|
- .in_rect.top = 0,
|
|
- .in_rect.width = 1920,
|
|
- .in_rect.height = 1088,
|
|
- .out_rect.left = 0,
|
|
- .out_rect.top = 0,
|
|
- .out_rect.width = 1920,
|
|
- .out_rect.height = 1088,
|
|
- },
|
|
- {
|
|
- .subdev_type = CRL_SUBDEV_TYPE_BINNER,
|
|
- .in_rect.left = 0,
|
|
- .in_rect.top = 0,
|
|
- .in_rect.width = 1920,
|
|
- .in_rect.height = 1088,
|
|
- .out_rect.left = 0,
|
|
- .out_rect.top = 0,
|
|
- .out_rect.width = 1920,
|
|
- .out_rect.height = 1088,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
|
|
- { 0x4d09, CRL_REG_LEN_08BIT, 0x5f },
|
|
- { 0x0104, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x0303, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x0305, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x0307, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x0316, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x0317, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x0323, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x0325, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x0326, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x032b, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x0400, CRL_REG_LEN_08BIT, 0xe7 },
|
|
- { 0x0401, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x0404, CRL_REG_LEN_08BIT, 0x2b },
|
|
- { 0x0405, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x0406, CRL_REG_LEN_08BIT, 0x33 },
|
|
- { 0x0407, CRL_REG_LEN_08BIT, 0x8f },
|
|
- { 0x0408, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x0410, CRL_REG_LEN_08BIT, 0xe7 },
|
|
- { 0x0411, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x0414, CRL_REG_LEN_08BIT, 0x2b },
|
|
- { 0x0415, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x0416, CRL_REG_LEN_08BIT, 0x33 },
|
|
- { 0x0417, CRL_REG_LEN_08BIT, 0x8f },
|
|
- { 0x0418, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3002, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x3012, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x3016, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3017, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3018, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3019, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x301a, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x301b, CRL_REG_LEN_08BIT, 0xb4 },
|
|
- { 0x301e, CRL_REG_LEN_08BIT, 0xb8 },
|
|
- { 0x301f, CRL_REG_LEN_08BIT, 0xe1 },
|
|
- { 0x3022, CRL_REG_LEN_08BIT, 0xf8 },
|
|
- { 0x3023, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3024, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3028, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3029, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x3706, CRL_REG_LEN_08BIT, 0x39 },
|
|
- { 0x370a, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x370b, CRL_REG_LEN_08BIT, 0xa3 },
|
|
- { 0x3712, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x3713, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3716, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x371d, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3721, CRL_REG_LEN_08BIT, 0x1c },
|
|
- { 0x372c, CRL_REG_LEN_08BIT, 0x17 },
|
|
- { 0x3733, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x3741, CRL_REG_LEN_08BIT, 0x44 },
|
|
- { 0x3742, CRL_REG_LEN_08BIT, 0x34 },
|
|
- { 0x3746, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x374b, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x3755, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x376c, CRL_REG_LEN_08BIT, 0x15 },
|
|
- { 0x376d, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x376f, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3770, CRL_REG_LEN_08BIT, 0x91 },
|
|
- { 0x3771, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3774, CRL_REG_LEN_08BIT, 0x82 },
|
|
- { 0x3777, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3779, CRL_REG_LEN_08BIT, 0x22 },
|
|
- { 0x377a, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x377b, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x377c, CRL_REG_LEN_08BIT, 0x48 },
|
|
- { 0x3785, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3790, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x3793, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x379c, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x37a1, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x37b3, CRL_REG_LEN_08BIT, 0x0a },
|
|
- { 0x37bb, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x37be, CRL_REG_LEN_08BIT, 0xe0 },
|
|
- { 0x37bf, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37c6, CRL_REG_LEN_08BIT, 0x48 },
|
|
- { 0x37c7, CRL_REG_LEN_08BIT, 0x38 },
|
|
- { 0x37c9, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37ca, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x37cb, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37cc, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x37d1, CRL_REG_LEN_08BIT, 0x39 },
|
|
- { 0x37d2, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37d3, CRL_REG_LEN_08BIT, 0xa3 },
|
|
- { 0x37d5, CRL_REG_LEN_08BIT, 0x39 },
|
|
- { 0x37d6, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37d7, CRL_REG_LEN_08BIT, 0xa3 },
|
|
- { 0x3c06, CRL_REG_LEN_08BIT, 0x29 },
|
|
- { 0x3c0b, CRL_REG_LEN_08BIT, 0xa8 },
|
|
- { 0x3c12, CRL_REG_LEN_08BIT, 0x89 },
|
|
- { 0x3c14, CRL_REG_LEN_08BIT, 0x81 },
|
|
- { 0x3c18, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3c3b, CRL_REG_LEN_08BIT, 0x38 },
|
|
- { 0x3c53, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3c55, CRL_REG_LEN_08BIT, 0xeb },
|
|
- { 0x3101, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x3192, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3193, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3206, CRL_REG_LEN_08BIT, 0xc8 },
|
|
- { 0x3216, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3304, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x3400, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3409, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3600, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3601, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3602, CRL_REG_LEN_08BIT, 0x42 },
|
|
- { 0x3603, CRL_REG_LEN_08BIT, 0xe3 },
|
|
- { 0x3604, CRL_REG_LEN_08BIT, 0x93 },
|
|
- { 0x3605, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x3606, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x3607, CRL_REG_LEN_08BIT, 0x4a },
|
|
- { 0x3608, CRL_REG_LEN_08BIT, 0x98 },
|
|
- { 0x3609, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x360a, CRL_REG_LEN_08BIT, 0x90 },
|
|
- { 0x360b, CRL_REG_LEN_08BIT, 0x0a },
|
|
- { 0x360e, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x3610, CRL_REG_LEN_08BIT, 0x89 },
|
|
- { 0x3611, CRL_REG_LEN_08BIT, 0x4b },
|
|
- { 0x3612, CRL_REG_LEN_08BIT, 0x4e },
|
|
- { 0x3619, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3620, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3621, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x3626, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x362c, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x362d, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x362e, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x362f, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3630, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3631, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3632, CRL_REG_LEN_08BIT, 0x99 },
|
|
- { 0x3633, CRL_REG_LEN_08BIT, 0x99 },
|
|
- { 0x3643, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3644, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3645, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x3646, CRL_REG_LEN_08BIT, 0x0f },
|
|
- { 0x3647, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x3648, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3649, CRL_REG_LEN_08BIT, 0x11 },
|
|
- { 0x364a, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x364c, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x364d, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x364e, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x364f, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x3652, CRL_REG_LEN_08BIT, 0xc5 },
|
|
- { 0x3654, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3656, CRL_REG_LEN_08BIT, 0xcf },
|
|
- { 0x3657, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x3658, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x365a, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x365b, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x365c, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x365d, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3660, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3661, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x3662, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3663, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x3665, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x3666, CRL_REG_LEN_08BIT, 0x13 },
|
|
- { 0x3667, CRL_REG_LEN_08BIT, 0x14 },
|
|
- { 0x3668, CRL_REG_LEN_08BIT, 0x95 },
|
|
- { 0x3669, CRL_REG_LEN_08BIT, 0x16 },
|
|
- { 0x366f, CRL_REG_LEN_08BIT, 0xc4 },
|
|
- { 0x3671, CRL_REG_LEN_08BIT, 0x37 },
|
|
- { 0x3673, CRL_REG_LEN_08BIT, 0x6a },
|
|
- { 0x3678, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x3800, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3801, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3802, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3803, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3804, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x3805, CRL_REG_LEN_08BIT, 0x8f },
|
|
- { 0x3806, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3807, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3808, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x3809, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x380a, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x380b, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x380f, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3810, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3813, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x381c, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3820, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3822, CRL_REG_LEN_08BIT, 0x14 },
|
|
- { 0x3832, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3833, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3834, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x383d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x384c, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x384d, CRL_REG_LEN_08BIT, 0x14 },
|
|
- { 0x384e, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x384f, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3850, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3851, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3852, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3853, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3854, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3855, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3856, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3857, CRL_REG_LEN_08BIT, 0x33 },
|
|
- { 0x3858, CRL_REG_LEN_08BIT, 0x7c },
|
|
- { 0x3859, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x385a, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x385b, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x385c, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x385f, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3860, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x3861, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3862, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3863, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3864, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3865, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3866, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3b40, CRL_REG_LEN_08BIT, 0x3e },
|
|
- { 0x3b41, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b42, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3b43, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b44, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b45, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x3b46, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b47, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x3b84, CRL_REG_LEN_08BIT, 0x36 },
|
|
- { 0x3b85, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b86, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b87, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x3b88, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b89, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x3b8a, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b8b, CRL_REG_LEN_08BIT, 0x0a },
|
|
- { 0x3b8e, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x3b8f, CRL_REG_LEN_08BIT, 0xe8 },
|
|
- { 0x3d85, CRL_REG_LEN_08BIT, 0x0b },
|
|
- { 0x3d8c, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d8d, CRL_REG_LEN_08BIT, 0x26 },
|
|
- { 0x3d97, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d98, CRL_REG_LEN_08BIT, 0x24 },
|
|
- { 0x3d99, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d9a, CRL_REG_LEN_08BIT, 0x6d },
|
|
- { 0x3d9b, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d9c, CRL_REG_LEN_08BIT, 0x6e },
|
|
- { 0x3d9d, CRL_REG_LEN_08BIT, 0x73 },
|
|
- { 0x3d9e, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x3e07, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3f00, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x4000, CRL_REG_LEN_08BIT, 0xf8 },
|
|
- { 0x4001, CRL_REG_LEN_08BIT, 0xeb },
|
|
- { 0x4004, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4005, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4008, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x4009, CRL_REG_LEN_08BIT, 0x0d },
|
|
- { 0x400a, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x400b, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x400f, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x4010, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x4011, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x4016, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4017, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x4018, CRL_REG_LEN_08BIT, 0x18 },
|
|
- { 0x401a, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x4028, CRL_REG_LEN_08BIT, 0x4f },
|
|
- { 0x402e, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x402f, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4030, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4031, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4032, CRL_REG_LEN_08BIT, 0x9e },
|
|
- { 0x4033, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x4308, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4501, CRL_REG_LEN_08BIT, 0x18 },
|
|
- { 0x4502, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4507, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x4580, CRL_REG_LEN_08BIT, 0xf8 },
|
|
- { 0x4581, CRL_REG_LEN_08BIT, 0xc7 },
|
|
- { 0x4582, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x4602, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4603, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x460a, CRL_REG_LEN_08BIT, 0x36 },
|
|
- { 0x460c, CRL_REG_LEN_08BIT, 0x60 },
|
|
- { 0x4700, CRL_REG_LEN_08BIT, 0x2a },
|
|
- { 0x470a, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x470b, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x4800, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x480e, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x4813, CRL_REG_LEN_08BIT, 0xd2 },
|
|
- { 0x4815, CRL_REG_LEN_08BIT, 0x2b },
|
|
- { 0x4837, CRL_REG_LEN_08BIT, 0x28 },
|
|
- { 0x484a, CRL_REG_LEN_08BIT, 0x3f },
|
|
- { 0x484b, CRL_REG_LEN_08BIT, 0x67 },
|
|
- { 0x4850, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4861, CRL_REG_LEN_08BIT, 0xa0 },
|
|
- { 0x4886, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4900, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x4903, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x4f00, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x4f01, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x4f05, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x5180, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5181, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5182, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5183, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5184, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5185, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5186, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5187, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a0, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a1, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a6, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c0, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c1, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c6, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5380, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5381, CRL_REG_LEN_08BIT, 0x94 },
|
|
- { 0x5382, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x53a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x53a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x53a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x53a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x53a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x53a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5400, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5401, CRL_REG_LEN_08BIT, 0x94 },
|
|
- { 0x5402, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x5420, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x5422, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5423, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5424, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5425, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5427, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5480, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5481, CRL_REG_LEN_08BIT, 0x94 },
|
|
- { 0x5482, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x54a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x54a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x54a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x54a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x54a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x54a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5800, CRL_REG_LEN_08BIT, 0x31 },
|
|
- { 0x5801, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5804, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5805, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x5806, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x5807, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x580e, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x5812, CRL_REG_LEN_08BIT, 0x34 },
|
|
- { 0x5000, CRL_REG_LEN_08BIT, 0x89 },
|
|
- { 0x5001, CRL_REG_LEN_08BIT, 0x42 },
|
|
- { 0x5002, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5003, CRL_REG_LEN_08BIT, 0x16 },
|
|
- { 0x503e, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x503f, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5602, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5603, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5604, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5605, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5606, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5607, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5608, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5609, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x560a, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x560b, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x560c, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x560d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x560e, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x560f, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5610, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5611, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5612, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5613, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5614, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5615, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5616, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5617, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5618, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5619, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5642, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5643, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5644, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5645, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5646, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5647, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5648, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5649, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x564a, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x564b, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x564c, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x564d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x564e, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x564f, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5650, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5651, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5652, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5653, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5654, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5655, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5656, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5657, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5658, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5659, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5682, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5683, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5684, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5685, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5686, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5687, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5688, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5689, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x568a, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x568b, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x568c, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x568d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x568e, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x568f, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5690, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5691, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5692, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5693, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5694, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5695, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5696, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5697, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5698, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5699, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5709, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x5749, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x5789, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x5200, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x5201, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x5202, CRL_REG_LEN_08BIT, 0x73 },
|
|
- { 0x5203, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x5205, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x5285, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x5305, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x5082, CRL_REG_LEN_08BIT, 0xb0 },
|
|
- { 0x50c2, CRL_REG_LEN_08BIT, 0xb0 },
|
|
- { 0x5102, CRL_REG_LEN_08BIT, 0xb0 },
|
|
- { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x380f, CRL_REG_LEN_08BIT, 0x34 },
|
|
- { 0x380c, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x380d, CRL_REG_LEN_08BIT, 0x78 },
|
|
- { 0x384c, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x384d, CRL_REG_LEN_08BIT, 0x14 },
|
|
- { 0x460a, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x0100, CRL_REG_LEN_08BIT, 0x01 },
|
|
-};
|
|
-
|
|
-static struct crl_register_write_rep ox03a10_1920_1088_12DCG_12VS[] = {
|
|
- { 0x4d09, CRL_REG_LEN_08BIT, 0x5f },
|
|
- { 0x0104, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x0303, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x0305, CRL_REG_LEN_08BIT, 0x36 },
|
|
- { 0x0307, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x0316, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x0317, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x0323, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x0325, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x0326, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x032b, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x0400, CRL_REG_LEN_08BIT, 0xe7 },
|
|
- { 0x0401, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x0404, CRL_REG_LEN_08BIT, 0x2b },
|
|
- { 0x0405, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x0406, CRL_REG_LEN_08BIT, 0x33 },
|
|
- { 0x0407, CRL_REG_LEN_08BIT, 0x8f },
|
|
- { 0x0408, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x0410, CRL_REG_LEN_08BIT, 0xe7 },
|
|
- { 0x0411, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x0414, CRL_REG_LEN_08BIT, 0x2b },
|
|
- { 0x0415, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x0416, CRL_REG_LEN_08BIT, 0x33 },
|
|
- { 0x0417, CRL_REG_LEN_08BIT, 0x8f },
|
|
- { 0x0418, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3002, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x3012, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x3016, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3017, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3018, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3019, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x301a, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x301b, CRL_REG_LEN_08BIT, 0xb4 },
|
|
- { 0x301e, CRL_REG_LEN_08BIT, 0xb8 },
|
|
- { 0x301f, CRL_REG_LEN_08BIT, 0xe1 },
|
|
- { 0x3022, CRL_REG_LEN_08BIT, 0xf8 },
|
|
- { 0x3023, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3024, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3028, CRL_REG_LEN_08BIT, 0xf0 },
|
|
- { 0x3029, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x3706, CRL_REG_LEN_08BIT, 0x39 },
|
|
- { 0x370a, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x370b, CRL_REG_LEN_08BIT, 0xa3 },
|
|
- { 0x3712, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x3713, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3716, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x371d, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3721, CRL_REG_LEN_08BIT, 0x1c },
|
|
- { 0x372c, CRL_REG_LEN_08BIT, 0x17 },
|
|
- { 0x3733, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x3741, CRL_REG_LEN_08BIT, 0x44 },
|
|
- { 0x3742, CRL_REG_LEN_08BIT, 0x34 },
|
|
- { 0x3746, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x374b, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x3755, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x376c, CRL_REG_LEN_08BIT, 0x15 },
|
|
- { 0x376d, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x376f, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3770, CRL_REG_LEN_08BIT, 0x91 },
|
|
- { 0x3771, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3774, CRL_REG_LEN_08BIT, 0x82 },
|
|
- { 0x3777, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3779, CRL_REG_LEN_08BIT, 0x22 },
|
|
- { 0x377a, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x377b, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x377c, CRL_REG_LEN_08BIT, 0x48 },
|
|
- { 0x3785, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3790, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x3793, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x379c, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x37a1, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x37b3, CRL_REG_LEN_08BIT, 0x0a },
|
|
- { 0x37bb, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x37be, CRL_REG_LEN_08BIT, 0xe0 },
|
|
- { 0x37bf, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37c6, CRL_REG_LEN_08BIT, 0x48 },
|
|
- { 0x37c7, CRL_REG_LEN_08BIT, 0x38 },
|
|
- { 0x37c9, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37ca, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x37cb, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37cc, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x37d1, CRL_REG_LEN_08BIT, 0x39 },
|
|
- { 0x37d2, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37d3, CRL_REG_LEN_08BIT, 0xa3 },
|
|
- { 0x37d5, CRL_REG_LEN_08BIT, 0x39 },
|
|
- { 0x37d6, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x37d7, CRL_REG_LEN_08BIT, 0xa3 },
|
|
- { 0x3c06, CRL_REG_LEN_08BIT, 0x29 },
|
|
- { 0x3c0b, CRL_REG_LEN_08BIT, 0xa8 },
|
|
- { 0x3c12, CRL_REG_LEN_08BIT, 0x89 },
|
|
- { 0x3c14, CRL_REG_LEN_08BIT, 0x81 },
|
|
- { 0x3c18, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3c3b, CRL_REG_LEN_08BIT, 0x38 },
|
|
- { 0x3c53, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3c55, CRL_REG_LEN_08BIT, 0xeb },
|
|
- { 0x3101, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x3192, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3193, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3206, CRL_REG_LEN_08BIT, 0xc8 },
|
|
- { 0x3216, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3304, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x3400, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3409, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3600, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3601, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3602, CRL_REG_LEN_08BIT, 0x42 },
|
|
- { 0x3603, CRL_REG_LEN_08BIT, 0xe3 },
|
|
- { 0x3604, CRL_REG_LEN_08BIT, 0x93 },
|
|
- { 0x3605, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x3606, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x3607, CRL_REG_LEN_08BIT, 0x4a },
|
|
- { 0x3608, CRL_REG_LEN_08BIT, 0x98 },
|
|
- { 0x3609, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x360a, CRL_REG_LEN_08BIT, 0xd0 },
|
|
- { 0x360b, CRL_REG_LEN_08BIT, 0x0b },
|
|
- { 0x360e, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x3610, CRL_REG_LEN_08BIT, 0x89 },
|
|
- { 0x3611, CRL_REG_LEN_08BIT, 0x4b },
|
|
- { 0x3612, CRL_REG_LEN_08BIT, 0x4e },
|
|
- { 0x3619, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3620, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3621, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x3626, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x362c, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x362d, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x362e, CRL_REG_LEN_08BIT, 0x0a },
|
|
- { 0x362f, CRL_REG_LEN_08BIT, 0x17 },
|
|
- { 0x3630, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x3631, CRL_REG_LEN_08BIT, 0x3f },
|
|
- { 0x3632, CRL_REG_LEN_08BIT, 0x99 },
|
|
- { 0x3633, CRL_REG_LEN_08BIT, 0x99 },
|
|
- { 0x3643, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3644, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3645, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x3646, CRL_REG_LEN_08BIT, 0x0f },
|
|
- { 0x3647, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x3648, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3649, CRL_REG_LEN_08BIT, 0x11 },
|
|
- { 0x364a, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x364c, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x364d, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x364e, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x364f, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x3652, CRL_REG_LEN_08BIT, 0xc5 },
|
|
- { 0x3654, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3656, CRL_REG_LEN_08BIT, 0xcf },
|
|
- { 0x3657, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x3658, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x365a, CRL_REG_LEN_08BIT, 0x3f },
|
|
- { 0x365b, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x365c, CRL_REG_LEN_08BIT, 0x17 },
|
|
- { 0x365d, CRL_REG_LEN_08BIT, 0x0a },
|
|
- { 0x3660, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3661, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x3662, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3663, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x3665, CRL_REG_LEN_08BIT, 0x12 },
|
|
- { 0x3666, CRL_REG_LEN_08BIT, 0x13 },
|
|
- { 0x3667, CRL_REG_LEN_08BIT, 0x14 },
|
|
- { 0x3668, CRL_REG_LEN_08BIT, 0x95 },
|
|
- { 0x3669, CRL_REG_LEN_08BIT, 0x16 },
|
|
- { 0x366f, CRL_REG_LEN_08BIT, 0xc4 },
|
|
- { 0x3671, CRL_REG_LEN_08BIT, 0x37 },
|
|
- { 0x3673, CRL_REG_LEN_08BIT, 0x6a },
|
|
- { 0x3678, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x3800, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3801, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3802, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3803, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3804, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x3805, CRL_REG_LEN_08BIT, 0x8f },
|
|
- { 0x3806, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3807, CRL_REG_LEN_08BIT, 0x0c },
|
|
- { 0x3808, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x3809, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x380a, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x380b, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x380f, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3810, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3813, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x381c, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x3820, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3822, CRL_REG_LEN_08BIT, 0x14 },
|
|
- { 0x3832, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3833, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3834, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x383d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x384c, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x384d, CRL_REG_LEN_08BIT, 0x14 },
|
|
- { 0x384e, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x384f, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3850, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3851, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3852, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x3853, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3854, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3855, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3856, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x3857, CRL_REG_LEN_08BIT, 0x33 },
|
|
- { 0x3858, CRL_REG_LEN_08BIT, 0x7c },
|
|
- { 0x3859, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x385a, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x385b, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x385c, CRL_REG_LEN_08BIT, 0x32 },
|
|
- { 0x385f, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3860, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x3861, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3862, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3863, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3864, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3865, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3866, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3b40, CRL_REG_LEN_08BIT, 0x3e },
|
|
- { 0x3b41, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b42, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x3b43, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b44, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b45, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x3b46, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b47, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x3b84, CRL_REG_LEN_08BIT, 0x36 },
|
|
- { 0x3b85, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b86, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b87, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x3b88, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b89, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x3b8a, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x3b8b, CRL_REG_LEN_08BIT, 0x0a },
|
|
- { 0x3b8e, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x3b8f, CRL_REG_LEN_08BIT, 0xe8 },
|
|
- { 0x3d85, CRL_REG_LEN_08BIT, 0x0b },
|
|
- { 0x3d8c, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d8d, CRL_REG_LEN_08BIT, 0x26 },
|
|
- { 0x3d97, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d98, CRL_REG_LEN_08BIT, 0x24 },
|
|
- { 0x3d99, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d9a, CRL_REG_LEN_08BIT, 0x6d },
|
|
- { 0x3d9b, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x3d9c, CRL_REG_LEN_08BIT, 0x6e },
|
|
- { 0x3d9d, CRL_REG_LEN_08BIT, 0x73 },
|
|
- { 0x3d9e, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x3e07, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x3f00, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x4000, CRL_REG_LEN_08BIT, 0xf8 },
|
|
- { 0x4001, CRL_REG_LEN_08BIT, 0xeb },
|
|
- { 0x4004, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4005, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4008, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x4009, CRL_REG_LEN_08BIT, 0x0d },
|
|
- { 0x400a, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x400b, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x400f, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x4010, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x4011, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x4016, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4017, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x4018, CRL_REG_LEN_08BIT, 0x18 },
|
|
- { 0x401a, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x4028, CRL_REG_LEN_08BIT, 0x4f },
|
|
- { 0x402e, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x402f, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4030, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4031, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4032, CRL_REG_LEN_08BIT, 0x9e },
|
|
- { 0x4033, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x4308, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4501, CRL_REG_LEN_08BIT, 0x18 },
|
|
- { 0x4502, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4507, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x4580, CRL_REG_LEN_08BIT, 0xf8 },
|
|
- { 0x4581, CRL_REG_LEN_08BIT, 0xc7 },
|
|
- { 0x4582, CRL_REG_LEN_08BIT, 0x07 },
|
|
- { 0x4602, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4603, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x460a, CRL_REG_LEN_08BIT, 0x36 },
|
|
- { 0x460c, CRL_REG_LEN_08BIT, 0x60 },
|
|
- { 0x4700, CRL_REG_LEN_08BIT, 0x2a },
|
|
- { 0x470a, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x470b, CRL_REG_LEN_08BIT, 0x88 },
|
|
- { 0x4800, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x480e, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x4813, CRL_REG_LEN_08BIT, 0xd2 },
|
|
- { 0x4815, CRL_REG_LEN_08BIT, 0x2b },
|
|
- { 0x4837, CRL_REG_LEN_08BIT, 0x18 },
|
|
- { 0x484a, CRL_REG_LEN_08BIT, 0x3f },
|
|
- { 0x484b, CRL_REG_LEN_08BIT, 0x67 },
|
|
- { 0x4850, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x4861, CRL_REG_LEN_08BIT, 0xa0 },
|
|
- { 0x4886, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x4900, CRL_REG_LEN_08BIT, 0x08 },
|
|
- { 0x4903, CRL_REG_LEN_08BIT, 0x80 },
|
|
- { 0x4f00, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x4f01, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x4f05, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x5180, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5181, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5182, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5183, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5184, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5185, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5186, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5187, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a0, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a1, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51a6, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c0, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c1, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x51c6, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x51c7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5380, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5381, CRL_REG_LEN_08BIT, 0x94 },
|
|
- { 0x5382, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x53a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x53a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x53a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x53a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x53a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x53a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5400, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5401, CRL_REG_LEN_08BIT, 0x94 },
|
|
- { 0x5402, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x5420, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x5422, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5423, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5424, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x5425, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5427, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5480, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5481, CRL_REG_LEN_08BIT, 0x94 },
|
|
- { 0x5482, CRL_REG_LEN_08BIT, 0x2e },
|
|
- { 0x54a0, CRL_REG_LEN_08BIT, 0x41 },
|
|
- { 0x54a2, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x54a3, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x54a4, CRL_REG_LEN_08BIT, 0x04 },
|
|
- { 0x54a5, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x54a7, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5800, CRL_REG_LEN_08BIT, 0x31 },
|
|
- { 0x5801, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5804, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5805, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x5806, CRL_REG_LEN_08BIT, 0x01 },
|
|
- { 0x5807, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x580e, CRL_REG_LEN_08BIT, 0x10 },
|
|
- { 0x5812, CRL_REG_LEN_08BIT, 0x34 },
|
|
- { 0x5000, CRL_REG_LEN_08BIT, 0x89 },
|
|
- { 0x5001, CRL_REG_LEN_08BIT, 0x42 },
|
|
- { 0x5002, CRL_REG_LEN_08BIT, 0x19 },
|
|
- { 0x5003, CRL_REG_LEN_08BIT, 0x16 },
|
|
- { 0x503e, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x503f, CRL_REG_LEN_08BIT, 0x00 },
|
|
- { 0x5602, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5603, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5604, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5605, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5606, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5607, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5608, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5609, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x560a, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x560b, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x560c, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x560d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x560e, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x560f, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5610, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5611, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5612, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5613, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5614, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5615, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5616, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5617, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5618, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5619, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5642, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5643, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5644, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5645, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5646, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5647, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5648, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5649, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x564a, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x564b, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x564c, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x564d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x564e, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x564f, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5650, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5651, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5652, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5653, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5654, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5655, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5656, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5657, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5658, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5659, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5682, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5683, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5684, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5685, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5686, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5687, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5688, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5689, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x568a, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x568b, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x568c, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x568d, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x568e, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x568f, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5690, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5691, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5692, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5693, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5694, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5695, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5696, CRL_REG_LEN_08BIT, 0x02 },
|
|
- { 0x5697, CRL_REG_LEN_08BIT, 0x58 },
|
|
- { 0x5698, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x5699, CRL_REG_LEN_08BIT, 0x20 },
|
|
- { 0x5709, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x5749, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x5789, CRL_REG_LEN_08BIT, 0x0e },
|
|
- { 0x5200, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x5201, CRL_REG_LEN_08BIT, 0x70 },
|
|
- { 0x5202, CRL_REG_LEN_08BIT, 0x73 },
|
|
- { 0x5203, CRL_REG_LEN_08BIT, 0xff },
|
|
- { 0x5205, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x5285, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x5305, CRL_REG_LEN_08BIT, 0x6c },
|
|
- { 0x5082, CRL_REG_LEN_08BIT, 0xb0 },
|
|
- { 0x50c2, CRL_REG_LEN_08BIT, 0xb0 },
|
|
- { 0x5102, CRL_REG_LEN_08BIT, 0xb0 },
|
|
- { 0x380e, CRL_REG_LEN_08BIT, 0x05 },
|
|
- { 0x380f, CRL_REG_LEN_08BIT, 0x34 },
|
|
- { 0x380c, CRL_REG_LEN_08BIT, 0x06 },
|
|
- { 0x380d, CRL_REG_LEN_08BIT, 0xcc },
|
|
- { 0x384c, CRL_REG_LEN_08BIT, 0x03 },
|
|
- { 0x384d, CRL_REG_LEN_08BIT, 0xc0 },
|
|
- { 0x460c, CRL_REG_LEN_08BIT, 0x40 },
|
|
- { 0x0100, CRL_REG_LEN_08BIT, 0x01 },
|
|
-};
|
|
-
|
|
-struct crl_ctrl_data_pair ox03a10_ctrl_data_modes[] = {
|
|
- {
|
|
- .ctrl_id = CRL_CID_EXPOSURE_MODE,
|
|
- .data = 0,
|
|
- },
|
|
- {
|
|
- .ctrl_id = CRL_CID_EXPOSURE_MODE,
|
|
- .data = 1,
|
|
- }
|
|
-};
|
|
-
|
|
-struct crl_mode_rep ox03a10_modes[] = {
|
|
- {
|
|
- .sd_rects_items = ARRAY_SIZE(ox03a10_1920_1088_rects),
|
|
- .sd_rects = ox03a10_1920_1088_rects,
|
|
- .binn_hor = 1,
|
|
- .binn_vert = 1,
|
|
- .scale_m = 1,
|
|
- .width = 1920,
|
|
- .height = 1088,
|
|
- .comp_items = 1,
|
|
- .ctrl_data = &ox03a10_ctrl_data_modes[0],
|
|
- .mode_regs_items = ARRAY_SIZE(ox03a10_1920_1088_12DCG),
|
|
- .mode_regs = ox03a10_1920_1088_12DCG,
|
|
- },
|
|
- {
|
|
- .sd_rects_items = ARRAY_SIZE(ox03a10_1920_1088_rects),
|
|
- .sd_rects = ox03a10_1920_1088_rects,
|
|
- .binn_hor = 1,
|
|
- .binn_vert = 1,
|
|
- .scale_m = 1,
|
|
- .width = 1920,
|
|
- .height = 1088,
|
|
- .comp_items = 1,
|
|
- .ctrl_data = &ox03a10_ctrl_data_modes[1],
|
|
- .mode_regs_items = ARRAY_SIZE(ox03a10_1920_1088_12DCG_12VS),
|
|
- .mode_regs = ox03a10_1920_1088_12DCG_12VS,
|
|
- },
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops bits_5_0[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_AND,
|
|
- .operand.entity_val = 0x3F,
|
|
- },
|
|
- {
|
|
- .op = CRL_BITWISE_LSHIFT,
|
|
- .operand.entity_val = 2,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops bits_10_6[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_RSHIFT,
|
|
- .operand.entity_val = 6,
|
|
- },
|
|
- {
|
|
- .op = CRL_BITWISE_AND,
|
|
- .operand.entity_val = 0x1F,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops bits_13_10[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_RSHIFT,
|
|
- .operand.entity_val = 10,
|
|
- },
|
|
- {
|
|
- .op = CRL_BITWISE_AND,
|
|
- .operand.entity_val = 0xF,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops bits_9_2[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_RSHIFT,
|
|
- .operand.entity_val = 2,
|
|
- },
|
|
- {
|
|
- .op = CRL_BITWISE_AND,
|
|
- .operand.entity_val = 0xFF,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops bits_1_0[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_AND,
|
|
- .operand.entity_val = 0x3,
|
|
- },
|
|
- {
|
|
- .op = CRL_BITWISE_LSHIFT,
|
|
- .operand.entity_val = 6,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops bits_15_8[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_RSHIFT,
|
|
- .operand.entity_val = 8,
|
|
- },
|
|
- {
|
|
- .op = CRL_BITWISE_AND,
|
|
- .operand.entity_val = 0xff,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops bits_7_0[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_AND,
|
|
- .operand.entity_val = 0xff,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_hcg_real_gain[] = {
|
|
- {
|
|
- .address = 0x3508,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_10_6),
|
|
- .ops = bits_10_6,
|
|
- },
|
|
- {
|
|
- .address = 0x3509,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_5_0),
|
|
- .ops = bits_5_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_hcg_digital_gain[] = {
|
|
- {
|
|
- .address = 0x350a,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_13_10),
|
|
- .ops = bits_13_10,
|
|
- },
|
|
- {
|
|
- .address = 0x350b,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_9_2),
|
|
- .ops = bits_9_2,
|
|
- },
|
|
- {
|
|
- .address = 0x350c,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_1_0),
|
|
- .ops = bits_1_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_lcg_real_gain[] = {
|
|
- {
|
|
- .address = 0x3548,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_10_6),
|
|
- .ops = bits_10_6,
|
|
- },
|
|
- {
|
|
- .address = 0x3549,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_5_0),
|
|
- .ops = bits_5_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_lcg_digital_gain[] = {
|
|
- {
|
|
- .address = 0x354a,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_13_10),
|
|
- .ops = bits_13_10,
|
|
- },
|
|
- {
|
|
- .address = 0x354b,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_9_2),
|
|
- .ops = bits_9_2,
|
|
- },
|
|
- {
|
|
- .address = 0x354c,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_1_0),
|
|
- .ops = bits_1_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_dcg_exposure_coarse[] = {
|
|
- {
|
|
- .address = 0x3501,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_15_8),
|
|
- .ops = bits_15_8,
|
|
- },
|
|
- {
|
|
- .address = 0x3502,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_7_0),
|
|
- .ops = bits_7_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_vs_real_gain[] = {
|
|
- {
|
|
- .address = 0x3588,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_10_6),
|
|
- .ops = bits_10_6,
|
|
- },
|
|
- {
|
|
- .address = 0x3589,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_5_0),
|
|
- .ops = bits_5_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_vs_digital_gain[] = {
|
|
- {
|
|
- .address = 0x358a,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_13_10),
|
|
- .ops = bits_13_10,
|
|
- },
|
|
- {
|
|
- .address = 0x358b,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_9_2),
|
|
- .ops = bits_9_2,
|
|
- },
|
|
- {
|
|
- .address = 0x358c,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_1_0),
|
|
- .ops = bits_1_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_vs_exposure_coarse[] = {
|
|
- {
|
|
- .address = 0x3581,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_15_8),
|
|
- .ops = bits_15_8,
|
|
- },
|
|
- {
|
|
- .address = 0x3582,
|
|
- .len = CRL_REG_LEN_08BIT,
|
|
- .ops_items = ARRAY_SIZE(bits_7_0),
|
|
- .ops = bits_7_0,
|
|
- }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops ox03a10_mirror_ops[] = {
|
|
- {
|
|
- .op = CRL_BITWISE_LSHIFT,
|
|
- .operand.entity_val = 2,
|
|
- },
|
|
- {
|
|
- .op = CRL_BITWISE_OR,
|
|
- .operand.entity_val = 0x20,
|
|
- },
|
|
-};
|
|
-
|
|
-static struct crl_dynamic_register_access ox03a10_h_flip_regs[] = {
|
|
- {
|
|
- .address = 0x3821,
|
|
- .len = CRL_REG_LEN_08BIT | CRL_REG_READ_AND_UPDATE,
|
|
- .ops_items = ARRAY_SIZE(ox03a10_mirror_ops),
|
|
- .ops = ox03a10_mirror_ops,
|
|
- .mask = 0x24,
|
|
- },
|
|
- {
|
|
- .address = 0x3811,
|
|
- .len = CRL_REG_LEN_08BIT | CRL_REG_READ_AND_UPDATE,
|
|
- .ops_items = 0,
|
|
- .ops = 0,
|
|
- .mask = 0x1,
|
|
- },
|
|
-};
|
|
-
|
|
-/* keep GRBG no change during flip, for tuning file handle GRBG only */
|
|
-static struct crl_flip_data ox03a10_flip_configurations[] = {
|
|
- {
|
|
- .flip = CRL_FLIP_DEFAULT_NONE,
|
|
- .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
- },
|
|
- {
|
|
- .flip = CRL_FLIP_HFLIP,
|
|
- .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
- },
|
|
-};
|
|
-
|
|
-struct crl_v4l2_ctrl ox03a10_v4l2_ctrls[] = {
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "DCG exposure",
|
|
- .ctrl_id = V4L2_CID_EXPOSURE,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 1,
|
|
- .data.std_data.max = 1280,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x40,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_dcg_exposure_coarse),
|
|
- .regs = ox03a10_dcg_exposure_coarse,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "VS exposure",
|
|
- .ctrl_id = CRL_CID_EXPOSURE_SHS1,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 1,
|
|
- .data.std_data.max = 1280,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x40,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_vs_exposure_coarse),
|
|
- .regs = ox03a10_vs_exposure_coarse,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "HCG digital gain",
|
|
- .ctrl_id = V4L2_CID_GAIN,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x400,
|
|
- .data.std_data.max = 0x3FFF,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x400,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_hcg_digital_gain),
|
|
- .regs = ox03a10_hcg_digital_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "HCG analog gain",
|
|
- .ctrl_id = V4L2_CID_ANALOGUE_GAIN,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x40,
|
|
- .data.std_data.max = 0x400,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x40,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_hcg_real_gain),
|
|
- .regs = ox03a10_hcg_real_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "HCG digital gain",
|
|
- .ctrl_id = V4L2_CID_DIGITAL_GAIN,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x400,
|
|
- .data.std_data.max = 0x3FFF,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x400,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_hcg_digital_gain),
|
|
- .regs = ox03a10_hcg_digital_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "LCG analog gain",
|
|
- .ctrl_id = CRL_CID_ANALOG_GAIN_S,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x40,
|
|
- .data.std_data.max = 0x400,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x40,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_lcg_real_gain),
|
|
- .regs = ox03a10_lcg_real_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "LCG digital gain",
|
|
- .ctrl_id = CRL_CID_DIGITAL_GAIN_S,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x400,
|
|
- .data.std_data.max = 0x3FFF,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x400,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_lcg_digital_gain),
|
|
- .regs = ox03a10_lcg_digital_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "LCG analog gain",
|
|
- .ctrl_id = CRL_CID_ANALOG_GAIN_L,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x40,
|
|
- .data.std_data.max = 0x400,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x40,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_lcg_real_gain),
|
|
- .regs = ox03a10_lcg_real_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "LCG digital gain",
|
|
- .ctrl_id = CRL_CID_DIGITAL_GAIN_L,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x400,
|
|
- .data.std_data.max = 0x3FFF,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x400,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_lcg_digital_gain),
|
|
- .regs = ox03a10_lcg_digital_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "VS analog gain",
|
|
- .ctrl_id = CRL_CID_ANALOG_GAIN_VS,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x40,
|
|
- .data.std_data.max = 0x400,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x40,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_vs_real_gain),
|
|
- .regs = ox03a10_vs_real_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "VS digital gain",
|
|
- .ctrl_id = CRL_CID_DIGITAL_GAIN_VS,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0x400,
|
|
- .data.std_data.max = 0x3FFF,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0x400,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_vs_digital_gain),
|
|
- .regs = ox03a10_vs_digital_gain,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .name = "CRL_CID_EXPOSURE_MODE",
|
|
- .ctrl_id = CRL_CID_EXPOSURE_MODE,
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 0,
|
|
- .data.std_data.max = 1,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_MODE_SELECTION,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_GET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .ctrl_id = V4L2_CID_PIXEL_RATE,
|
|
- .name = "V4L2_CID_PIXEL_RATE_PA",
|
|
- .type = CRL_V4L2_CTRL_TYPE_INTEGER,
|
|
- .data.std_data.min = 0,
|
|
- .data.std_data.max = INT_MAX,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0,
|
|
- .flags = 0,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = 0,
|
|
- .regs = 0,
|
|
- .dep_items = 0,
|
|
- .dep_ctrls = 0,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .ctrl_id = V4L2_CID_LINE_LENGTH_PIXELS,
|
|
- .name = "Line Length Pixels",
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 1920,
|
|
- .data.std_data.max = 65535,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 2700,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .ctrl = 0,
|
|
- .regs_items = ARRAY_SIZE(ar0231at_llp_regs),
|
|
- .regs = ar0231at_llp_regs,
|
|
- .dep_items = 0,
|
|
- .dep_ctrls = 0,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .ctrl_id = V4L2_CID_FRAME_LENGTH_LINES,
|
|
- .name = "Frame Length Lines",
|
|
- .type = CRL_V4L2_CTRL_TYPE_CUSTOM,
|
|
- .data.std_data.min = 1088,
|
|
- .data.std_data.max = 65535,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 1480,
|
|
- .flags = V4L2_CTRL_FLAG_UPDATE,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .ctrl = 0,
|
|
- .regs_items = ARRAY_SIZE(ar0231at_fll_regs),
|
|
- .regs = ar0231at_fll_regs,
|
|
- .dep_items = 0,
|
|
- .dep_ctrls = 0,
|
|
- .v4l2_type = V4L2_CTRL_TYPE_INTEGER,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .ctrl_id = V4L2_CID_HFLIP,
|
|
- .name = "V4L2_CID_HFLIP",
|
|
- .type = CRL_V4L2_CTRL_TYPE_INTEGER,
|
|
- .data.std_data.min = 0,
|
|
- .data.std_data.max = 1,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 1,
|
|
- .flags = 0,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .ctrl = 0,
|
|
- .regs_items = ARRAY_SIZE(ox03a10_h_flip_regs),
|
|
- .regs = ox03a10_h_flip_regs,
|
|
- .dep_items = 0,
|
|
- .dep_ctrls = 0,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_BINNER,
|
|
- .op_type = CRL_V4L2_CTRL_GET_OP,
|
|
- .context = SENSOR_POWERED_ON,
|
|
- .ctrl_id = V4L2_CID_PIXEL_RATE,
|
|
- .name = "V4L2_CID_PIXEL_RATE_CSI",
|
|
- .type = CRL_V4L2_CTRL_TYPE_INTEGER,
|
|
- .data.std_data.min = 0,
|
|
- .data.std_data.max = INT_MAX,
|
|
- .data.std_data.step = 1,
|
|
- .data.std_data.def = 0,
|
|
- .flags = 0,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = 0,
|
|
- .regs = 0,
|
|
- .dep_items = 0,
|
|
- .dep_ctrls = 0,
|
|
- },
|
|
- {
|
|
- .sd_type = CRL_SUBDEV_TYPE_BINNER,
|
|
- .op_type = CRL_V4L2_CTRL_SET_OP,
|
|
- .context = SENSOR_IDLE,
|
|
- .ctrl_id = V4L2_CID_LINK_FREQ,
|
|
- .name = "V4L2_CID_LINK_FREQ",
|
|
- .type = CRL_V4L2_CTRL_TYPE_MENU_INT,
|
|
- .data.v4l2_int_menu.def = 0,
|
|
- .data.v4l2_int_menu.max = 0,
|
|
- .data.v4l2_int_menu.menu = 0,
|
|
- .flags = 0,
|
|
- .impact = CRL_IMPACTS_NO_IMPACT,
|
|
- .regs_items = 0,
|
|
- .regs = 0,
|
|
- .dep_items = 0,
|
|
- .dep_ctrls = 0,
|
|
- },
|
|
-};
|
|
-
|
|
-struct crl_csi_data_fmt ox03a10_crl_csi_data_fmt[] = {
|
|
- {
|
|
- .code = MEDIA_BUS_FMT_SGRBG12_1X12,
|
|
- .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
- .bits_per_pixel = 12,
|
|
- .regs_items = 0,
|
|
- .regs = 0,
|
|
- },
|
|
-};
|
|
-
|
|
-struct crl_pll_configuration ox03a10_pll_configurations[] = {
|
|
- {
|
|
- .input_clk = 27000000,
|
|
- .op_sys_clk = 108000000,
|
|
- .bitsperpixel = 12,
|
|
- .pixel_rate_csi = 108000000,
|
|
- .pixel_rate_pa = 108000000, /* pixel_rate = op_sys_clk*2 *csi_lanes/bitsperpixel */
|
|
- .csi_lanes = 4,
|
|
- .comp_items = 0,
|
|
- .ctrl_data = 0,
|
|
- .pll_regs_items = 0,
|
|
- .pll_regs = 0,
|
|
- },
|
|
-};
|
|
-
|
|
-static struct crl_register_write_rep ox03a10_streamoff_regs[] = {
|
|
- { 0x0100, CRL_REG_LEN_08BIT, 0x00 }
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops ox03a10_frame_desc_width_ops[] = {
|
|
- {
|
|
- .op = CRL_ASSIGNMENT,
|
|
- .operand.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_VAR_REF,
|
|
- .operand.entity_val = CRL_VAR_REF_OUTPUT_WIDTH,
|
|
- },
|
|
-};
|
|
-
|
|
-static struct crl_arithmetic_ops ox03a10_frame_desc_height_ops[] = {
|
|
- {
|
|
- .op = CRL_ASSIGNMENT,
|
|
- .operand.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_CONST,
|
|
- .operand.entity_val = 1,
|
|
- },
|
|
-};
|
|
-
|
|
-static struct crl_frame_desc ox03a10_frame_desc[] = {
|
|
- {
|
|
- .flags.entity_val = 0,
|
|
- .bpp.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_VAR_REF,
|
|
- .bpp.entity_val = CRL_VAR_REF_BITSPERPIXEL,
|
|
- .pixelcode.entity_val = MEDIA_BUS_FMT_FIXED,
|
|
- .length.entity_val = 0,
|
|
- .start_line.entity_val = 0,
|
|
- .start_pixel.entity_val = 0,
|
|
- .width = {
|
|
- .ops_items = ARRAY_SIZE(ox03a10_frame_desc_width_ops),
|
|
- .ops = ox03a10_frame_desc_width_ops,
|
|
- },
|
|
- .height = {
|
|
- .ops_items = ARRAY_SIZE(ox03a10_frame_desc_height_ops),
|
|
- .ops = ox03a10_frame_desc_height_ops,
|
|
- },
|
|
- .csi2_channel.entity_val = 0,
|
|
- .csi2_data_type.entity_val = 0x12,
|
|
- },
|
|
- {
|
|
- .flags.entity_val = 0,
|
|
- .bpp.entity_type = CRL_DYNAMIC_VAL_OPERAND_TYPE_VAR_REF,
|
|
- .bpp.entity_val = CRL_VAR_REF_BITSPERPIXEL,
|
|
- .pixelcode.entity_val = MEDIA_BUS_FMT_FIXED,
|
|
- .length.entity_val = 0,
|
|
- .start_line.entity_val = 0,
|
|
- .start_pixel.entity_val = 0,
|
|
- .width = {
|
|
- .ops_items = ARRAY_SIZE(ox03a10_frame_desc_width_ops),
|
|
- .ops = ox03a10_frame_desc_width_ops,
|
|
- },
|
|
- .height = {
|
|
- .ops_items = ARRAY_SIZE(ox03a10_frame_desc_height_ops),
|
|
- .ops = ox03a10_frame_desc_height_ops,
|
|
- },
|
|
- .csi2_channel.entity_val = 1,
|
|
- .csi2_data_type.entity_val = 0x12,
|
|
- },
|
|
-};
|
|
-
|
|
struct crl_sensor_configuration ox03a10_crl_configuration = {
|
|
.pll_config_items = ARRAY_SIZE(ox03a10_pll_configurations),
|
|
.pll_configs = ox03a10_pll_configurations,
|
|
diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h b/drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h
|
|
new file mode 100644
|
|
index 000000000000..eaf262852608
|
|
--- /dev/null
|
|
+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_ficosa_configuration.h
|
|
@@ -0,0 +1,57 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0 */
|
|
+/* Copyright (C) 2018 Intel Corporation
|
|
+ *
|
|
+ * Author: Chang Ying <ying.chang@intel.com>
|
|
+ *
|
|
+ */
|
|
+
|
|
+#ifndef __CRLMODULE_OX03A10_FICOSA_CONFIGURATION_H_
|
|
+#define __CRLMODULE_OX03A10_FICOSA_CONFIGURATION_H_
|
|
+
|
|
+#include "crlmodule-sensor-ds.h"
|
|
+#include "crl_ox03a10_common.h"
|
|
+
|
|
+struct crl_sensor_subdev_config ox03a10_ficosa_sensor_subdevs[] = {
|
|
+ {
|
|
+ .subdev_type = CRL_SUBDEV_TYPE_BINNER,
|
|
+ .name = "ox03a10_ficosa binner",
|
|
+ },
|
|
+ {
|
|
+ .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .name = "ox03a10_ficosa pixel array",
|
|
+ }
|
|
+};
|
|
+
|
|
+struct crl_sensor_configuration ox03a10_ficosa_crl_configuration = {
|
|
+ .pll_config_items = ARRAY_SIZE(ox03a10_pll_configurations),
|
|
+ .pll_configs = ox03a10_pll_configurations,
|
|
+
|
|
+ .id_reg_items = ARRAY_SIZE(ox03a10_sensor_detect_regset),
|
|
+ .id_regs = ox03a10_sensor_detect_regset,
|
|
+
|
|
+ .subdev_items = ARRAY_SIZE(ox03a10_ficosa_sensor_subdevs),
|
|
+ .subdevs = ox03a10_ficosa_sensor_subdevs,
|
|
+
|
|
+ .sensor_limits = &ox03a10_sensor_limits,
|
|
+
|
|
+ .modes_items = ARRAY_SIZE(ox03a10_modes),
|
|
+ .modes = ox03a10_modes,
|
|
+
|
|
+ .v4l2_ctrls_items = ARRAY_SIZE(ox03a10_v4l2_ctrls),
|
|
+ .v4l2_ctrl_bank = ox03a10_v4l2_ctrls,
|
|
+
|
|
+ .csi_fmts_items = ARRAY_SIZE(ox03a10_crl_csi_data_fmt),
|
|
+ .csi_fmts = ox03a10_crl_csi_data_fmt,
|
|
+
|
|
+ .flip_items = ARRAY_SIZE(ox03a10_flip_configurations),
|
|
+ .flip_data = ox03a10_flip_configurations,
|
|
+
|
|
+ .streamoff_regs_items = ARRAY_SIZE(ox03a10_streamoff_regs),
|
|
+ .streamoff_regs = ox03a10_streamoff_regs,
|
|
+
|
|
+ .frame_desc_entries = ARRAY_SIZE(ox03a10_frame_desc),
|
|
+ .frame_desc_type = CRL_V4L2_MBUS_FRAME_DESC_TYPE_CSI2,
|
|
+ .frame_desc = ox03a10_frame_desc,
|
|
+};
|
|
+
|
|
+#endif /* __CRLMODULE_OX03A10_FICOSA_CONFIGURATION_H_ */
|
|
diff --git a/drivers/media/i2c/crlmodule/crlmodule-data.c b/drivers/media/i2c/crlmodule/crlmodule-data.c
|
|
index 2c07ca06a83a..d6a370a16746 100644
|
|
--- a/drivers/media/i2c/crlmodule/crlmodule-data.c
|
|
+++ b/drivers/media/i2c/crlmodule/crlmodule-data.c
|
|
@@ -32,6 +32,7 @@
|
|
#include "crl_ar023z_configuration.h"
|
|
#include "crl_ov2775_configuration.h"
|
|
#include "crl_ox03a10_configuration.h"
|
|
+#include "crl_ox03a10_ficosa_configuration.h"
|
|
#include "crl_ov495_configuration.h"
|
|
|
|
static const struct crlmodule_sensors supported_sensors[] = {
|
|
@@ -71,6 +72,8 @@ static const struct crlmodule_sensors supported_sensors[] = {
|
|
{ "AR023Z", "ar023z", &ar023z_crl_configuration },
|
|
{ "OV2775", "ov2775", &ov2775_crl_configuration },
|
|
{ "OX03A10", "ox03a10", &ox03a10_crl_configuration },
|
|
+ { "OX03A10_FICOSA", "ox03a10_ficosa",
|
|
+ &ox03a10_ficosa_crl_configuration },
|
|
{ "OV495", "ov495", &ov495_crl_configuration},
|
|
};
|
|
|
|
--
|
|
https://clearlinux.org
|
|
|