68 lines
2.3 KiB
Diff
68 lines
2.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Min He <min.he@intel.com>
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Date: Thu, 13 Jun 2019 03:27:22 +0000
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Subject: [PATCH] drm/i915/gvt: fix some garbage display issue in plane
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restriction
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In plane restriction case, when ServiceOS updates the plane wm
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registers, sometimes there's garbage appears because the guest doesn't
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update its plane registers in the same vblank period after plane wm
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registers updated.
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This patch will force refresh the plane registers (PLANE_CTL and
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PLANE_SURF) owned by guests, after the wm registers updated.
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Signed-off-by: Min He <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 39cef1485a2e..57a676e8dfe5 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -5599,6 +5599,28 @@ skl_compute_wm(struct drm_atomic_state *state)
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return 0;
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}
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+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
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+/*
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+ * when SOS updates plane wm registers, we need to refresh the planes owned by
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+ * GVT-g guests, to avoid some garbage display on the screen
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+ */
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+static void update_gvt_guest_plane(struct drm_i915_private *dev_priv,
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+ int pipe,
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+ int plane_id)
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+{
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+ unsigned long value, irqflags;
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+
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+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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+
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+ value = I915_READ_FW(PLANE_CTL(pipe, plane_id));
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+ I915_WRITE_FW(PLANE_CTL(pipe, plane_id), value);
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+ value = I915_READ_FW(PLANE_SURF(pipe, plane_id));
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+ I915_WRITE_FW(PLANE_SURF(pipe, plane_id), value);
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+
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+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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+}
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+#endif
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+
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static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
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struct intel_crtc_state *cstate)
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{
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@@ -5621,6 +5643,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
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for_each_universal_plane(dev_priv, pipe, plane_id) {
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skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
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ddb, plane_id);
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+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
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+ if (dev_priv->gvt &&
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+ dev_priv->gvt->pipe_info[pipe].plane_owner[plane_id])
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+ update_gvt_guest_plane(dev_priv, pipe, plane_id);
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+#endif
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}
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return;
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--
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https://clearlinux.org
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