43 lines
1.4 KiB
Diff
43 lines
1.4 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Ong Hock Yu <ong.hock.yu@intel.com>
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Date: Thu, 16 May 2019 06:05:30 +0000
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Subject: [PATCH] media: intel-ipu4: [ICI/VIRT] Fix top half and bottom half
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ISR race condition
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Under race condition, the bottom half of the ISR get finished
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before top half and this caused the state get overwritten.
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The fix is to move all the state update in top half to before
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bottom half get started.
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Change-Id: I95e7325c07d576495f63b393a4816d9336d508c8
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Tracked-On: PKT-2287
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Tracked-On: HSDES-1507210582
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Signed-off-by: Ong Hock Yu <ong.hock.yu@intel.com>
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---
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drivers/media/pci/intel/virtio/intel-ipu4-virtio-be-bridge.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/drivers/media/pci/intel/virtio/intel-ipu4-virtio-be-bridge.c b/drivers/media/pci/intel/virtio/intel-ipu4-virtio-be-bridge.c
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index 19ffac6e2110..e40f7149abcf 100644
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--- a/drivers/media/pci/intel/virtio/intel-ipu4-virtio-be-bridge.c
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+++ b/drivers/media/pci/intel/virtio/intel-ipu4-virtio-be-bridge.c
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@@ -38,6 +38,8 @@ int intel_ipu4_virtio_msg_parse(struct ipu4_virtio_req_info *req_info)
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return -EINVAL;
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}
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+ req->stat = IPU4_REQ_PENDING;
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+
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switch (req->cmd) {
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case IPU4_CMD_POLL:
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/*
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@@ -250,6 +252,5 @@ int intel_ipu4_virtio_msg_parse(struct ipu4_virtio_req_info *req_info)
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return -EINVAL;
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}
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- req->stat = IPU4_REQ_PENDING;
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return ret;
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}
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--
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https://clearlinux.org
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