50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
|
From: "He, Min" <min.he@intel.com>
|
|
Date: Fri, 22 Feb 2019 02:23:55 +0000
|
|
Subject: [PATCH] drm/i915/gvt: add PIPEDSL to pvmmio trap list to read HW
|
|
PIPEDSL register for guest
|
|
|
|
The PipeDSL register will be read in irq handler. But currently it
|
|
is accessed based on write-protected mode after PVMMIO is enabled.
|
|
This patch added PIPEDSL registers to the pvmmio trap list so that guest
|
|
will be able to read the HW PIPEDSL registers. This patch can help to
|
|
reduce the time consumption of vblank irq handler in guest.
|
|
|
|
Change-Id: Ie9d2fa0125db9dadd5475fa8aeb036cde2adb90d
|
|
Tracked-On: projectacrn/acrn-hypervisor#2597
|
|
Signed-off-by: He, Min <min.he@intel.com>
|
|
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
|
|
Tracked-On: PKT-1750
|
|
---
|
|
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
|
|
1 file changed, 7 insertions(+)
|
|
|
|
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
|
|
index d9e2fb75e5b3..32bcdb94cc6b 100644
|
|
--- a/drivers/gpu/drm/i915/i915_reg.h
|
|
+++ b/drivers/gpu/drm/i915/i915_reg.h
|
|
@@ -5648,6 +5648,9 @@ enum {
|
|
#define PIPE_B_OFFSET 0x71000
|
|
#define PIPE_C_OFFSET 0x72000
|
|
#define CHV_PIPE_C_OFFSET 0x74000
|
|
+
|
|
+#define __PIPEBDSL 0x71000
|
|
+#define __PIPECDSL 0x72000
|
|
/*
|
|
* There's actually no pipe EDP. Some pipe registers have
|
|
* simply shifted from the pipe to the transcoder, while
|
|
@@ -10691,6 +10694,10 @@ static inline bool in_mmio_read_trap_list(u32 reg)
|
|
if (unlikely(reg == SBI_DATA.reg || reg == 0x6c060 || reg == 0x206c))
|
|
return true;
|
|
|
|
+ if (unlikely(reg == _PIPEADSL ||
|
|
+ reg == __PIPEBDSL ||
|
|
+ reg == __PIPECDSL))
|
|
+ return true;
|
|
return false;
|
|
}
|
|
|
|
--
|
|
https://clearlinux.org
|
|
|