3732 lines
132 KiB
Diff
3732 lines
132 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: kgopala2 <karthik.l.gopalakrishnan@intel.com>
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Date: Sat, 29 Dec 2018 04:38:51 +0800
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Subject: [PATCH] media: intel-ipu4: [ICI] MAX9286 and AR0231AT enabled for ICI
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Add support of MAX9286 GMSL bridge and AR0231AT camera sensor
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Change-Id: I4b6b20222e4c22e057f4a08be9d7d20f58fb6270
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Tracked-On: PKT-1644
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Tracked-On: OAM-74863
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Signed-off-by: kgopala2 <karthik.l.gopalakrishnan@intel.com>
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---
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.../crl_ar0231at_configuration.h | 2411 +++++++++++++++++
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.../media/i2c/crlmodule-lite/crlmodule-data.c | 2 +
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drivers/media/i2c/ici/Kconfig | 6 +
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drivers/media/i2c/ici/Makefile | 1 +
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drivers/media/i2c/ici/max9286_ici.c | 1103 ++++++++
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.../platform/intel/ipu4-ici-bxt-p-pdata.c | 93 +-
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include/media/ici.h | 5 +
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7 files changed, 3620 insertions(+), 1 deletion(-)
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create mode 100644 drivers/media/i2c/crlmodule-lite/crl_ar0231at_configuration.h
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create mode 100644 drivers/media/i2c/ici/max9286_ici.c
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diff --git a/drivers/media/i2c/crlmodule-lite/crl_ar0231at_configuration.h b/drivers/media/i2c/crlmodule-lite/crl_ar0231at_configuration.h
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new file mode 100644
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index 000000000000..7ea3560f33c7
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--- /dev/null
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+++ b/drivers/media/i2c/crlmodule-lite/crl_ar0231at_configuration.h
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@@ -0,0 +1,2411 @@
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+/*
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+ * Copyright (c) 2018 Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License version
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+ * 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+
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+#ifndef __CRLMODULE_AR0231AT_CONFIGURATION_H_
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+#define __CRLMODULE_AR0231AT_CONFIGURATION_H_
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+
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+#include "crlmodule-sensor-ds.h"
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+
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+struct crl_pll_configuration ar0231at_pll_configurations[] = {
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+ {
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+ .input_clk = 27000000,
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+ .op_sys_clk = 87750000,
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+ .bitsperpixel = 12,
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+ .pixel_rate_csi = 176000000,
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+ .pixel_rate_pa = 176000000, /* pixel_rate = op_sys_clk*2 *csi_lanes/bitsperpixel */
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+ .csi_lanes = 4,
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+ .comp_items = 0,
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+ .ctrl_data = 0,
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+ .pll_regs_items = 0,
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+ .pll_regs = 0,
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+ },
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+ {
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+ .input_clk = 27000000,
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+ .op_sys_clk = 87750000,
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+ .bitsperpixel = 10,
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+ .pixel_rate_csi = 211200000,
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+ .pixel_rate_pa = 211200000, /* pixel_rate = op_sys_clk*2 *csi_lanes/bitsperpixel */
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+ .csi_lanes = 4,
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+ .comp_items = 0,
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+ .ctrl_data = 0,
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+ .pll_regs_items = 0,
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+ .pll_regs = 0,
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+ },
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+};
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+
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+struct crl_sensor_subdev_config ar0231at_sensor_subdevs[] = {
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_BINNER,
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+ .name = "ar0231at binner",
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+ },
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
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+ .name = "ar0231at pixel array",
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+ },
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+};
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+
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+struct crl_subdev_rect_rep ar0231at_1920_1088_rects[] = {
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
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+ .in_rect.left = 0,
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+ .in_rect.top = 0,
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+ .in_rect.width = 1920,
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+ .in_rect.height = 1088,
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+ .out_rect.left = 0,
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+ .out_rect.top = 0,
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+ .out_rect.width = 1920,
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+ .out_rect.height = 1088,
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+ },
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+ {
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+ .subdev_type = CRL_SUBDEV_TYPE_BINNER,
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+ .in_rect.left = 0,
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+ .in_rect.top = 0,
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+ .in_rect.width = 1920,
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+ .in_rect.height = 1088,
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+ .out_rect.left = 0,
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+ .out_rect.top = 0,
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+ .out_rect.width = 1920,
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+ .out_rect.height = 1088,
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+ }
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+};
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+
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+/*
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+ * Exposure mode:
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+ * 0: Linear mode
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+ * 1: 2-HDR mode
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+ * 2: 3-HDR mode
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+ * 3: 4-HDR mode
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+ */
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+struct crl_ctrl_data_pair ar0231at_ctrl_data_modes[] = {
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+ {
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+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE,
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+ .data = 0,
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+ },
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+ {
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+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE,
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+ .data = 1,
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+ },
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+ {
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+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE,
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+ .data = 2,
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+ },
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+ {
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+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE,
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+ .data = 3,
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+ },
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+ {
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+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE,
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+ .data = 4,
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+ },
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+};
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+
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+static struct crl_register_write_rep ar0231at_1920_1088_10bit_linear_mode[] = {
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+ { 0x301A, CRL_REG_LEN_16BIT, 0x1058, 0x10 },
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+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
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+ { 0x3092, CRL_REG_LEN_16BIT, 0x0C24, 0x10 },
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+ { 0x337A, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
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+ { 0x3520, CRL_REG_LEN_16BIT, 0x1288, 0x10 },
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+ { 0x3522, CRL_REG_LEN_16BIT, 0x880C, 0x10 },
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+ { 0x3524, CRL_REG_LEN_16BIT, 0x0C12, 0x10 },
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+ { 0x352C, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
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+ { 0x354A, CRL_REG_LEN_16BIT, 0x007F, 0x10 },
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+ { 0x350C, CRL_REG_LEN_16BIT, 0x055C, 0x10 },
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+ { 0x3506, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
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+ { 0x3508, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
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+ { 0x3100, CRL_REG_LEN_16BIT, 0x4000, 0x10 },
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+ { 0x3280, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3282, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3284, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3286, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3288, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x328A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x328C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x328E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3290, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3292, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3294, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3296, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x3298, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x329A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x329C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x329E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
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+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
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+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
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+ { 0x2512, CRL_REG_LEN_16BIT, 0x8000, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x3350, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x2004, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1578, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x7B24, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xEA24, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1022, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x2410, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x155A, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x24EA, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x2324, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x647A, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x2404, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x052C, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x400A, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1008, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x3851, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0801, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0408, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1180, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x2652, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1518, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0906, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1348, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1002, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1016, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1181, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1189, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0D09, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1413, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x2B15, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0311, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xD909, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1409, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0110, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xD612, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1012, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1011, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xDD11, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xD910, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x5609, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xDB09, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x9B09, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0F11, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1A12, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1014, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x6012, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x5010, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x7610, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xE609, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0812, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x4012, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x6009, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x290B, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0904, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0923, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x15C8, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x13C8, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x092C, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1388, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C09, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C14, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1112, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x6212, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x6011, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xBF11, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB10, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x6611, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xFB09, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x3511, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x6312, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x6014, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0015, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xB812, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xA012, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x2610, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0013, 0x10 },
|
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x3053, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x4215, 0x10 },
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|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4013, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x4010, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0210, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1611, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x8111, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x8910, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x5612, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1009, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x010D, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0815, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xD013, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x5009, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x1313, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xD009, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0x0215, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xC813, 0x10 },
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+ { 0x2510, CRL_REG_LEN_16BIT, 0xC009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0515, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0213, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0411, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0814, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD908, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x091A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0903, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10D6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11D9, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0917, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0913, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x121A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1250, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1076, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10E6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1240, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0925, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13AD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0902, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0907, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x138D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0914, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B13, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1C0C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0920, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1262, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1066, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x090A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x093B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1263, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1508, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11B8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x12A0, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1200, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1026, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1300, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1100, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x437A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B05, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0708, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4137, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x502C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2CFE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15FE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C2C, 0x10 },
|
|
+ { 0x32E6, CRL_REG_LEN_16BIT, 0x00E0, 0x10 },
|
|
+ { 0x1008, CRL_REG_LEN_16BIT, 0x036F, 0x10 },
|
|
+ { 0x100C, CRL_REG_LEN_16BIT, 0x058F, 0x10 },
|
|
+ { 0x100E, CRL_REG_LEN_16BIT, 0x07AF, 0x10 },
|
|
+ { 0x1010, CRL_REG_LEN_16BIT, 0x014F, 0x10 },
|
|
+ { 0x3230, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x3232, CRL_REG_LEN_16BIT, 0x0532, 0x10 },
|
|
+ { 0x3234, CRL_REG_LEN_16BIT, 0x0752, 0x10 },
|
|
+ { 0x3236, CRL_REG_LEN_16BIT, 0x00F2, 0x10 },
|
|
+ { 0x3566, CRL_REG_LEN_16BIT, 0x3328, 0x10 },
|
|
+ { 0x32D0, CRL_REG_LEN_16BIT, 0x3A02, 0x10 },
|
|
+ { 0x32D2, CRL_REG_LEN_16BIT, 0x3508, 0x10 },
|
|
+ { 0x32D4, CRL_REG_LEN_16BIT, 0x3702, 0x10 },
|
|
+ { 0x32D6, CRL_REG_LEN_16BIT, 0x3C04, 0x10 },
|
|
+ { 0x32DC, CRL_REG_LEN_16BIT, 0x370A, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x302A, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x302C, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x302E, CRL_REG_LEN_16BIT, 0x0003, 0x10 },
|
|
+ { 0x3030, CRL_REG_LEN_16BIT, 0x004E, 0x10 },
|
|
+ { 0x3036, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3038, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x30A2, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30A6, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3180, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E4, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3004, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x3008, CRL_REG_LEN_16BIT, 0x0783, 0x10 },
|
|
+ { 0x3002, CRL_REG_LEN_16BIT, 0x003C, 0x10 },
|
|
+ { 0x3006, CRL_REG_LEN_16BIT, 0x047B, 0x10 },
|
|
+ { 0x3032, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3400, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0F10, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x0970, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F1, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F0, 0x10 },
|
|
+ { 0x300C, CRL_REG_LEN_16BIT, 0x0872, 0x10 },
|
|
+ { 0x300A, CRL_REG_LEN_16BIT, 0x054A, 0x10 },
|
|
+ { 0x3042, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3012, CRL_REG_LEN_16BIT, 0x0163, 0x10 },
|
|
+ { 0x3014, CRL_REG_LEN_16BIT, 0x014F, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C08, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x31D0, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AC, CRL_REG_LEN_16BIT, 0x0C0A, 0x10 },
|
|
+ /* try sync mode */
|
|
+ { 0x340A, CRL_REG_LEN_16BIT, 0x0077, 0x10 },
|
|
+ { 0x340C, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x30CE, CRL_REG_LEN_16BIT, 0x0120, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x19DC, 0x10 },
|
|
+ { 0x3370, CRL_REG_LEN_16BIT, 0x0231, 0x10 },
|
|
+};
|
|
+
|
|
+static struct crl_register_write_rep ar0231at_1920_1088_linear_mode[] = {
|
|
+#if 0
|
|
+ { 0x300C, CRL_REG_LEN_16BIT, 0x0872, 0x10 },
|
|
+ { 0x300A, CRL_REG_LEN_16BIT, 0x05C8, 0x10 },
|
|
+ { 0x3366, CRL_REG_LEN_16BIT, 0xAAAA, 0x10 },
|
|
+ { 0x305E, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3012, CRL_REG_LEN_16BIT, 0x0163, 0x10 },
|
|
+ { 0x3212, CRL_REG_LEN_16BIT, 0x0002, 0x10 },
|
|
+ { 0x3216, CRL_REG_LEN_16BIT, 0x0002, 0x10 },
|
|
+ { 0x321A, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3070, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+#endif
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x1058, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
|
|
+ { 0x3092, CRL_REG_LEN_16BIT, 0x0C24, 0x10 },
|
|
+ { 0x337A, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3520, CRL_REG_LEN_16BIT, 0x1288, 0x10 },
|
|
+ { 0x3522, CRL_REG_LEN_16BIT, 0x880C, 0x10 },
|
|
+ { 0x3524, CRL_REG_LEN_16BIT, 0x0C12, 0x10 },
|
|
+ { 0x352C, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x354A, CRL_REG_LEN_16BIT, 0x007F, 0x10 },
|
|
+ { 0x350C, CRL_REG_LEN_16BIT, 0x055C, 0x10 },
|
|
+ { 0x3506, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3508, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3100, CRL_REG_LEN_16BIT, 0x4000, 0x10 },
|
|
+ { 0x3280, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3282, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3284, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3286, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3288, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3290, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3292, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3294, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3296, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3298, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
|
|
+ { 0x2512, CRL_REG_LEN_16BIT, 0x8000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3350, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1578, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7B24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xEA24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1022, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2410, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x155A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24EA, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2324, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x647A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2404, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x052C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x400A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3851, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0801, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0408, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1180, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2652, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1518, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0906, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1348, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1002, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1016, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1181, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1189, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0D09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1413, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2B15, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0311, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1409, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0110, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDD11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x9B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0F11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1A12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xE609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x290B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0904, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0923, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x092C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1388, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C14, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1112, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBF11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB10, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xB812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xA012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3053, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8111, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x010D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0815, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1313, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0515, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0213, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0411, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0814, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD908, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x091A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0903, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10D6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11D9, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0917, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0913, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x121A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1250, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1076, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10E6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1240, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0925, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13AD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0902, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0907, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x138D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0914, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B13, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1C0C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0920, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1262, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1066, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x090A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x093B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1263, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1508, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11B8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x12A0, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1200, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1026, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1300, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1100, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x437A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B05, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0708, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4137, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x502C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2CFE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15FE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C2C, 0x10 },
|
|
+ { 0x32E6, CRL_REG_LEN_16BIT, 0x00E0, 0x10 },
|
|
+ { 0x1008, CRL_REG_LEN_16BIT, 0x036F, 0x10 },
|
|
+ { 0x100C, CRL_REG_LEN_16BIT, 0x058F, 0x10 },
|
|
+ { 0x100E, CRL_REG_LEN_16BIT, 0x07AF, 0x10 },
|
|
+ { 0x1010, CRL_REG_LEN_16BIT, 0x014F, 0x10 },
|
|
+ { 0x3230, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x3232, CRL_REG_LEN_16BIT, 0x0532, 0x10 },
|
|
+ { 0x3234, CRL_REG_LEN_16BIT, 0x0752, 0x10 },
|
|
+ { 0x3236, CRL_REG_LEN_16BIT, 0x00F2, 0x10 },
|
|
+ { 0x3566, CRL_REG_LEN_16BIT, 0x3328, 0x10 },
|
|
+ { 0x32D0, CRL_REG_LEN_16BIT, 0x3A02, 0x10 },
|
|
+ { 0x32D2, CRL_REG_LEN_16BIT, 0x3508, 0x10 },
|
|
+ { 0x32D4, CRL_REG_LEN_16BIT, 0x3702, 0x10 },
|
|
+ { 0x32D6, CRL_REG_LEN_16BIT, 0x3C04, 0x10 },
|
|
+ { 0x32DC, CRL_REG_LEN_16BIT, 0x370A, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x302A, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x302C, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x302E, CRL_REG_LEN_16BIT, 0x0003, 0x10 },
|
|
+ { 0x3030, CRL_REG_LEN_16BIT, 0x004E, 0x10 },
|
|
+ { 0x3036, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3038, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x30A2, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30A6, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3180, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E4, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3004, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x3008, CRL_REG_LEN_16BIT, 0x0783, 0x10 },
|
|
+ { 0x3002, CRL_REG_LEN_16BIT, 0x003C, 0x10 },
|
|
+ { 0x3006, CRL_REG_LEN_16BIT, 0x047B, 0x10 },
|
|
+ { 0x3032, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3400, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0F10, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x0970, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F1, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F0, 0x10 },
|
|
+ { 0x300C, CRL_REG_LEN_16BIT, 0x0872, 0x10 },
|
|
+ { 0x300A, CRL_REG_LEN_16BIT, 0x054A, 0x10 },
|
|
+ { 0x3042, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3012, CRL_REG_LEN_16BIT, 0x0163, 0x10 },
|
|
+ { 0x3014, CRL_REG_LEN_16BIT, 0x014F, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C08, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x31D0, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AC, CRL_REG_LEN_16BIT, 0x0C0C, 0x10 },
|
|
+ /* try sync mode */
|
|
+ { 0x340A, CRL_REG_LEN_16BIT, 0x0077, 0x10 },
|
|
+ { 0x340C, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x30CE, CRL_REG_LEN_16BIT, 0x0120, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x19DC, 0x10 },
|
|
+ { 0x3370, CRL_REG_LEN_16BIT, 0x0231, 0x10 },
|
|
+};
|
|
+
|
|
+static struct crl_register_write_rep ar0231at_1920_1088_2hdr_mode[] = {
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 100, 0x10 },
|
|
+ { 0x3092, CRL_REG_LEN_16BIT, 0x0C24, 0x10 },
|
|
+ { 0x337A, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3520, CRL_REG_LEN_16BIT, 0x1288, 0x10 },
|
|
+ { 0x3522, CRL_REG_LEN_16BIT, 0x880C, 0x10 },
|
|
+ { 0x3524, CRL_REG_LEN_16BIT, 0x0C12, 0x10 },
|
|
+ { 0x352C, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x354A, CRL_REG_LEN_16BIT, 0x007F, 0x10 },
|
|
+ { 0x350C, CRL_REG_LEN_16BIT, 0x055C, 0x10 },
|
|
+ { 0x3506, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3508, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3100, CRL_REG_LEN_16BIT, 0x4000, 0x10 },
|
|
+ { 0x3280, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3282, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3284, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3286, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3288, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3290, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3292, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3294, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3296, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3298, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
|
|
+ { 0x2512, CRL_REG_LEN_16BIT, 0x8000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3350, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1578, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7B24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xEA24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1022, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2410, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x155A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24EA, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2324, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x647A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2404, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x052C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x400A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3851, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0801, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0408, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1180, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2652, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1518, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0906, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1348, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1002, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1016, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1181, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1189, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0D09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1413, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2B15, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0311, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1409, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0110, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDD11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x9B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0F11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1A12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xE609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x290B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0904, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0923, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x092C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1388, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C14, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1112, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBF11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB10, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xB812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xA012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3053, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8111, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x010D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0815, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1313, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0515, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0213, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0411, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0814, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD908, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x091A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0903, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10D6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11D9, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0917, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0913, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x121A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1250, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1076, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10E6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1240, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0925, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13AD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0902, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0907, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x138D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0914, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B13, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1C0C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0920, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1262, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1066, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x090A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x093B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1263, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1508, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11B8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x12A0, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1200, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1026, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1300, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1100, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x437A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B05, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0708, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4137, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x502C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2CFE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15FE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C2C, 0x10 },
|
|
+ { 0x32E6, CRL_REG_LEN_16BIT, 0x00E0, 0x10 },
|
|
+ { 0x1008, CRL_REG_LEN_16BIT, 0x036F, 0x10 },
|
|
+ { 0x100C, CRL_REG_LEN_16BIT, 0x058F, 0x10 },
|
|
+ { 0x100E, CRL_REG_LEN_16BIT, 0x07AF, 0x10 },
|
|
+ { 0x1010, CRL_REG_LEN_16BIT, 0x014F, 0x10 },
|
|
+ { 0x3230, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x3232, CRL_REG_LEN_16BIT, 0x0532, 0x10 },
|
|
+ { 0x3234, CRL_REG_LEN_16BIT, 0x0752, 0x10 },
|
|
+ { 0x3236, CRL_REG_LEN_16BIT, 0x00F2, 0x10 },
|
|
+ { 0x3566, CRL_REG_LEN_16BIT, 0x3328, 0x10 },
|
|
+ { 0x32D0, CRL_REG_LEN_16BIT, 0x3A02, 0x10 },
|
|
+ { 0x32D2, CRL_REG_LEN_16BIT, 0x3508, 0x10 },
|
|
+ { 0x32D4, CRL_REG_LEN_16BIT, 0x3702, 0x10 },
|
|
+ { 0x32D6, CRL_REG_LEN_16BIT, 0x3C04, 0x10 },
|
|
+ { 0x32DC, CRL_REG_LEN_16BIT, 0x370A, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x302A, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x302C, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x302E, CRL_REG_LEN_16BIT, 0x0003, 0x10 },
|
|
+ { 0x3030, CRL_REG_LEN_16BIT, 0x004E, 0x10 },
|
|
+ { 0x3036, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3038, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x30A2, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30A6, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F1, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x33C0, CRL_REG_LEN_16BIT, 0x2000, 0x10 },
|
|
+ { 0x33C2, CRL_REG_LEN_16BIT, 0x3440, 0x10 },
|
|
+ { 0x33C4, CRL_REG_LEN_16BIT, 0x4890, 0x10 },
|
|
+ { 0x33C6, CRL_REG_LEN_16BIT, 0x5CE0, 0x10 },
|
|
+ { 0x33C8, CRL_REG_LEN_16BIT, 0x7140, 0x10 },
|
|
+ { 0x33CA, CRL_REG_LEN_16BIT, 0x8590, 0x10 },
|
|
+ { 0x33CC, CRL_REG_LEN_16BIT, 0x99E0, 0x10 },
|
|
+ { 0x33CE, CRL_REG_LEN_16BIT, 0xAE40, 0x10 },
|
|
+ { 0x33D0, CRL_REG_LEN_16BIT, 0xC290, 0x10 },
|
|
+ { 0x33D2, CRL_REG_LEN_16BIT, 0xD6F0, 0x10 },
|
|
+ { 0x33D4, CRL_REG_LEN_16BIT, 0xEB40, 0x10 },
|
|
+ { 0x33D6, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x33DA, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3180, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E4, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3004, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x3008, CRL_REG_LEN_16BIT, 0x0783, 0x10 },
|
|
+ { 0x3002, CRL_REG_LEN_16BIT, 0x003C, 0x10 },
|
|
+ { 0x3006, CRL_REG_LEN_16BIT, 0x047B, 0x10 },
|
|
+ { 0x3032, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3400, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0788, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0F10, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x04B8, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x0970, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F1, 0x10 },
|
|
+ { 0x300C, CRL_REG_LEN_16BIT, 0x0872, 0x10 },
|
|
+ { 0x300A, CRL_REG_LEN_16BIT, 0x054A, 0x10 },
|
|
+ { 0x3042, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3012, CRL_REG_LEN_16BIT, 0x0163, 0x10 },
|
|
+ { 0x3014, CRL_REG_LEN_16BIT, 0x0882, 0x10 },
|
|
+ { 0x321E, CRL_REG_LEN_16BIT, 0x0882, 0x10 },
|
|
+ { 0x3222, CRL_REG_LEN_16BIT, 0x0882, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x31D0, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0201, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AC, CRL_REG_LEN_16BIT, 0x140C, 0x10 },
|
|
+ { 0x340A, CRL_REG_LEN_16BIT, 0x0077, 0x10 },
|
|
+ { 0x340C, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x30CE, CRL_REG_LEN_16BIT, 0x0120, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x19DC, 0x10 },
|
|
+ { 0x3370, CRL_REG_LEN_16BIT, 0x0231, 0x10 },
|
|
+};
|
|
+
|
|
+static struct crl_register_write_rep ar0231at_1920_1088_3hdr_mode[] = {
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 100, 0x10 },
|
|
+ { 0x3092, CRL_REG_LEN_16BIT, 0x0C24, 0x10 },
|
|
+ { 0x337A, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3520, CRL_REG_LEN_16BIT, 0x1288, 0x10 },
|
|
+ { 0x3522, CRL_REG_LEN_16BIT, 0x880C, 0x10 },
|
|
+ { 0x3524, CRL_REG_LEN_16BIT, 0x0C12, 0x10 },
|
|
+ { 0x352C, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x354A, CRL_REG_LEN_16BIT, 0x007F, 0x10 },
|
|
+ { 0x350C, CRL_REG_LEN_16BIT, 0x055C, 0x10 },
|
|
+ { 0x3506, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3508, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3100, CRL_REG_LEN_16BIT, 0x4000, 0x10 },
|
|
+ { 0x3280, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3282, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3284, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3286, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3288, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3290, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3292, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3294, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3296, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3298, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
|
|
+ { 0x2512, CRL_REG_LEN_16BIT, 0x8000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3350, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1578, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7B24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xEA24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1022, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2410, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x155A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24EA, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2324, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x647A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2404, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x052C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x400A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3851, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0801, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0408, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1180, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2652, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1518, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0906, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1348, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1002, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1016, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1181, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1189, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0D09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1413, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2B15, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0311, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1409, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0110, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDD11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x9B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0F11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1A12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xE609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x290B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0904, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0923, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x092C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1388, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C14, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1112, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBF11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB10, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xB812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xA012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3053, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8111, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x010D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0815, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1313, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0515, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0213, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0411, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0814, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD908, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x091A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0903, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10D6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11D9, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0917, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0913, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x121A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1250, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1076, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10E6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1240, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0925, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13AD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0902, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0907, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x138D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0914, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B13, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1C0C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0920, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1262, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1066, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x090A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x093B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1263, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1508, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11B8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x12A0, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1200, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1026, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1300, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1100, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x437A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B05, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0708, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4137, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x502C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2CFE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15FE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C2C, 0x10 },
|
|
+ { 0x32E6, CRL_REG_LEN_16BIT, 0x00E0, 0x10 },
|
|
+ { 0x1008, CRL_REG_LEN_16BIT, 0x036F, 0x10 },
|
|
+ { 0x100C, CRL_REG_LEN_16BIT, 0x058F, 0x10 },
|
|
+ { 0x100E, CRL_REG_LEN_16BIT, 0x07AF, 0x10 },
|
|
+ { 0x1010, CRL_REG_LEN_16BIT, 0x014F, 0x10 },
|
|
+ { 0x3230, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x3232, CRL_REG_LEN_16BIT, 0x0532, 0x10 },
|
|
+ { 0x3234, CRL_REG_LEN_16BIT, 0x0752, 0x10 },
|
|
+ { 0x3236, CRL_REG_LEN_16BIT, 0x00F2, 0x10 },
|
|
+ { 0x3566, CRL_REG_LEN_16BIT, 0x3328, 0x10 },
|
|
+ { 0x32D0, CRL_REG_LEN_16BIT, 0x3A02, 0x10 },
|
|
+ { 0x32D2, CRL_REG_LEN_16BIT, 0x3508, 0x10 },
|
|
+ { 0x32D4, CRL_REG_LEN_16BIT, 0x3702, 0x10 },
|
|
+ { 0x32D6, CRL_REG_LEN_16BIT, 0x3C04, 0x10 },
|
|
+ { 0x32DC, CRL_REG_LEN_16BIT, 0x370A, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x302A, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x302C, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x302E, CRL_REG_LEN_16BIT, 0x0003, 0x10 },
|
|
+ { 0x3030, CRL_REG_LEN_16BIT, 0x004E, 0x10 },
|
|
+ { 0x3036, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3038, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x30A2, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30A6, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x33C0, CRL_REG_LEN_16BIT, 0x2000, 0x10 },
|
|
+ { 0x33C2, CRL_REG_LEN_16BIT, 0x3440, 0x10 },
|
|
+ { 0x33C4, CRL_REG_LEN_16BIT, 0x4890, 0x10 },
|
|
+ { 0x33C6, CRL_REG_LEN_16BIT, 0x5CE0, 0x10 },
|
|
+ { 0x33C8, CRL_REG_LEN_16BIT, 0x7140, 0x10 },
|
|
+ { 0x33CA, CRL_REG_LEN_16BIT, 0x8590, 0x10 },
|
|
+ { 0x33CC, CRL_REG_LEN_16BIT, 0x99E0, 0x10 },
|
|
+ { 0x33CE, CRL_REG_LEN_16BIT, 0xAE40, 0x10 },
|
|
+ { 0x33D0, CRL_REG_LEN_16BIT, 0xC290, 0x10 },
|
|
+ { 0x33D2, CRL_REG_LEN_16BIT, 0xD6F0, 0x10 },
|
|
+ { 0x33D4, CRL_REG_LEN_16BIT, 0xEB40, 0x10 },
|
|
+ { 0x33D6, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x33DA, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3180, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E4, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3004, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x3008, CRL_REG_LEN_16BIT, 0x0783, 0x10 },
|
|
+ { 0x3002, CRL_REG_LEN_16BIT, 0x003C, 0x10 },
|
|
+ { 0x3006, CRL_REG_LEN_16BIT, 0x047B, 0x10 },
|
|
+ { 0x3032, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3400, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0788, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0F10, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x04B8, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x0970, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x300C, CRL_REG_LEN_16BIT, 0x0872, 0x10 },
|
|
+ { 0x300A, CRL_REG_LEN_16BIT, 0x054A, 0x10 },
|
|
+ { 0x3042, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3012, CRL_REG_LEN_16BIT, 0x0163, 0x10 },
|
|
+ { 0x3014, CRL_REG_LEN_16BIT, 0x0882, 0x10 },
|
|
+ { 0x321E, CRL_REG_LEN_16BIT, 0x0882, 0x10 },
|
|
+ { 0x3222, CRL_REG_LEN_16BIT, 0x0882, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x31D0, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0201, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AC, CRL_REG_LEN_16BIT, 0x140C, 0x10 },
|
|
+ { 0x340A, CRL_REG_LEN_16BIT, 0x0077, 0x10 },
|
|
+ { 0x340C, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x30CE, CRL_REG_LEN_16BIT, 0x0120, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x19DC, 0x10 },
|
|
+ { 0x3370, CRL_REG_LEN_16BIT, 0x0231, 0x10 },
|
|
+};
|
|
+
|
|
+static struct crl_register_write_rep ar0231at_1920_1088_4hdr_mode[] = {
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 100, 0x10 },
|
|
+ { 0x3092, CRL_REG_LEN_16BIT, 0x0C24, 0x10 },
|
|
+ { 0x337A, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3520, CRL_REG_LEN_16BIT, 0x1288, 0x10 },
|
|
+ { 0x3522, CRL_REG_LEN_16BIT, 0x880C, 0x10 },
|
|
+ { 0x3524, CRL_REG_LEN_16BIT, 0x0C12, 0x10 },
|
|
+ { 0x352C, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x354A, CRL_REG_LEN_16BIT, 0x007F, 0x10 },
|
|
+ { 0x350C, CRL_REG_LEN_16BIT, 0x055C, 0x10 },
|
|
+ { 0x3506, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3508, CRL_REG_LEN_16BIT, 0x3333, 0x10 },
|
|
+ { 0x3100, CRL_REG_LEN_16BIT, 0x4000, 0x10 },
|
|
+ { 0x3280, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3282, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3284, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3286, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3288, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x328E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3290, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3292, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3294, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3296, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x3298, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329A, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329C, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x329E, CRL_REG_LEN_16BIT, 0x0FA0, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x10D8, 0x10 },
|
|
+ { 0x0000, CRL_REG_LEN_DELAY, 200, 0x10 },
|
|
+ { 0x2512, CRL_REG_LEN_16BIT, 0x8000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3350, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1578, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7B24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xEA24, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1022, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2410, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x155A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24FF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x24EA, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2324, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x647A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2404, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x052C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x400A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFF0A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3851, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0801, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0408, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1180, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2652, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1518, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0906, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1348, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1002, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1016, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1181, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1189, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0D09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1413, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2B15, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0311, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1409, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0110, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDD11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xDB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x9B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0F11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1A12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x7610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xE609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x290B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0904, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0923, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13C8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x092C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1388, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C14, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1112, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBF11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB10, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xFB09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3511, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xBB12, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6312, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x6014, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xB812, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xA012, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2610, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0011, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x3053, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4010, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1611, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8111, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8910, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5612, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x010D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0815, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD013, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x5009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1313, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0215, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC015, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0515, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8813, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0213, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0411, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xC909, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0814, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0109, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B11, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0xD908, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x091A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1440, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0903, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1214, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10D6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1212, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11D9, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1056, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0917, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11DB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0913, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0905, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x121A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1210, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1460, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1250, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1076, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x10E6, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13A8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1240, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0925, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x13AD, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0902, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0907, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1588, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0901, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x138D, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B09, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0914, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4009, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B13, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x8809, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1C0C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0920, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1262, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BF, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1066, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x090A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11FB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x093B, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11BB, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1263, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1260, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1400, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1508, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x11B8, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x12A0, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1200, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1026, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1000, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1300, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x1100, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x437A, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0609, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0B05, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0708, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x4137, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x502C, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x2CFE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x15FE, 0x10 },
|
|
+ { 0x2510, CRL_REG_LEN_16BIT, 0x0C2C, 0x10 },
|
|
+ { 0x32E6, CRL_REG_LEN_16BIT, 0x00E0, 0x10 },
|
|
+ { 0x1008, CRL_REG_LEN_16BIT, 0x036F, 0x10 },
|
|
+ { 0x100C, CRL_REG_LEN_16BIT, 0x058F, 0x10 },
|
|
+ { 0x100E, CRL_REG_LEN_16BIT, 0x07AF, 0x10 },
|
|
+ { 0x1010, CRL_REG_LEN_16BIT, 0x014F, 0x10 },
|
|
+ { 0x3230, CRL_REG_LEN_16BIT, 0x0312, 0x10 },
|
|
+ { 0x3232, CRL_REG_LEN_16BIT, 0x0532, 0x10 },
|
|
+ { 0x3234, CRL_REG_LEN_16BIT, 0x0752, 0x10 },
|
|
+ { 0x3236, CRL_REG_LEN_16BIT, 0x00F2, 0x10 },
|
|
+ { 0x3566, CRL_REG_LEN_16BIT, 0x3328, 0x10 },
|
|
+ { 0x32D0, CRL_REG_LEN_16BIT, 0x3A02, 0x10 },
|
|
+ { 0x32D2, CRL_REG_LEN_16BIT, 0x3508, 0x10 },
|
|
+ { 0x32D4, CRL_REG_LEN_16BIT, 0x3702, 0x10 },
|
|
+ { 0x32D6, CRL_REG_LEN_16BIT, 0x3C04, 0x10 },
|
|
+ { 0x32DC, CRL_REG_LEN_16BIT, 0x370A, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x302A, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x302C, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x302E, CRL_REG_LEN_16BIT, 0x0003, 0x10 },
|
|
+ { 0x3030, CRL_REG_LEN_16BIT, 0x004E, 0x10 },
|
|
+ { 0x3036, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3038, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x30A2, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x30A6, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3040, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x0008, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F2, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3044, CRL_REG_LEN_16BIT, 0x0400, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x3064, CRL_REG_LEN_16BIT, 0x1802, 0x10 },
|
|
+ { 0x33C0, CRL_REG_LEN_16BIT, 0x2000, 0x10 },
|
|
+ { 0x33C2, CRL_REG_LEN_16BIT, 0x3440, 0x10 },
|
|
+ { 0x33C4, CRL_REG_LEN_16BIT, 0x4890, 0x10 },
|
|
+ { 0x33C6, CRL_REG_LEN_16BIT, 0x5CE0, 0x10 },
|
|
+ { 0x33C8, CRL_REG_LEN_16BIT, 0x7140, 0x10 },
|
|
+ { 0x33CA, CRL_REG_LEN_16BIT, 0x8590, 0x10 },
|
|
+ { 0x33CC, CRL_REG_LEN_16BIT, 0x99E0, 0x10 },
|
|
+ { 0x33CE, CRL_REG_LEN_16BIT, 0xAE40, 0x10 },
|
|
+ { 0x33D0, CRL_REG_LEN_16BIT, 0xC290, 0x10 },
|
|
+ { 0x33D2, CRL_REG_LEN_16BIT, 0xD6F0, 0x10 },
|
|
+ { 0x33D4, CRL_REG_LEN_16BIT, 0xEB40, 0x10 },
|
|
+ { 0x33D6, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x33DA, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3180, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E4, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x33E0, CRL_REG_LEN_16BIT, 0x0C80, 0x10 },
|
|
+ { 0x3004, CRL_REG_LEN_16BIT, 0x0004, 0x10 },
|
|
+ { 0x3008, CRL_REG_LEN_16BIT, 0x0783, 0x10 },
|
|
+ { 0x3002, CRL_REG_LEN_16BIT, 0x003C, 0x10 },
|
|
+ { 0x3006, CRL_REG_LEN_16BIT, 0x047B, 0x10 },
|
|
+ { 0x3032, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3400, CRL_REG_LEN_16BIT, 0x0010, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0788, 0x10 },
|
|
+ { 0x3402, CRL_REG_LEN_16BIT, 0x0F10, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x04B8, 0x10 },
|
|
+ { 0x3404, CRL_REG_LEN_16BIT, 0x0970, 0x10 },
|
|
+ { 0x3082, CRL_REG_LEN_16BIT, 0x000C, 0x10 },
|
|
+ { 0x30BA, CRL_REG_LEN_16BIT, 0x11F3, 0x10 },
|
|
+ { 0x300C, CRL_REG_LEN_16BIT, 0x09B8, 0x10 },
|
|
+ { 0x300A, CRL_REG_LEN_16BIT, 0x0498, 0x10 },
|
|
+ { 0x3042, CRL_REG_LEN_16BIT, 0x0000, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3238, CRL_REG_LEN_16BIT, 0x0222, 0x10 },
|
|
+ { 0x3012, CRL_REG_LEN_16BIT, 0x0131, 0x10 },
|
|
+ { 0x3014, CRL_REG_LEN_16BIT, 0x098E, 0x10 },
|
|
+ { 0x321E, CRL_REG_LEN_16BIT, 0x098E, 0x10 },
|
|
+ { 0x3222, CRL_REG_LEN_16BIT, 0x098E, 0x10 },
|
|
+ { 0x3226, CRL_REG_LEN_16BIT, 0x098E, 0x10 },
|
|
+ { 0x30B0, CRL_REG_LEN_16BIT, 0x0800, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EA, CRL_REG_LEN_16BIT, 0x3C0E, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x32EC, CRL_REG_LEN_16BIT, 0x72A1, 0x10 },
|
|
+ { 0x31D0, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0201, 0x10 },
|
|
+ { 0x31AE, CRL_REG_LEN_16BIT, 0x0001, 0x10 },
|
|
+ { 0x31AC, CRL_REG_LEN_16BIT, 0x140C, 0x10 },
|
|
+ { 0x340A, CRL_REG_LEN_16BIT, 0x0077, 0x10 },
|
|
+ { 0x340C, CRL_REG_LEN_16BIT, 0x0080, 0x10 },
|
|
+ { 0x30CE, CRL_REG_LEN_16BIT, 0x0120, 0x10 },
|
|
+ { 0x301A, CRL_REG_LEN_16BIT, 0x19DC, 0x10 },
|
|
+ { 0x3370, CRL_REG_LEN_16BIT, 0x0231, 0x10 },
|
|
+};
|
|
+
|
|
+struct crl_mode_rep ar0231at_modes[] = {
|
|
+ {
|
|
+ .sd_rects_items = ARRAY_SIZE(ar0231at_1920_1088_rects),
|
|
+ .sd_rects = ar0231at_1920_1088_rects,
|
|
+ .binn_hor = 1,
|
|
+ .binn_vert = 1,
|
|
+ .scale_m = 1,
|
|
+ .width = 1920,
|
|
+ .height = 1088,
|
|
+ .min_llp = 2162,
|
|
+ .min_fll = 1354,
|
|
+ .comp_items = 1,
|
|
+ .ctrl_data = &ar0231at_ctrl_data_modes[0],
|
|
+ .mode_regs_items = ARRAY_SIZE(ar0231at_1920_1088_linear_mode),
|
|
+ .mode_regs = ar0231at_1920_1088_linear_mode,
|
|
+ },
|
|
+ {
|
|
+ .sd_rects_items = ARRAY_SIZE(ar0231at_1920_1088_rects),
|
|
+ .sd_rects = ar0231at_1920_1088_rects,
|
|
+ .binn_hor = 1,
|
|
+ .binn_vert = 1,
|
|
+ .scale_m = 1,
|
|
+ .width = 1920,
|
|
+ .height = 1088,
|
|
+ .min_llp = 1978,
|
|
+ .min_fll = 1480,
|
|
+ .comp_items = 1,
|
|
+ .ctrl_data = &ar0231at_ctrl_data_modes[1],
|
|
+ .mode_regs_items = ARRAY_SIZE(ar0231at_1920_1088_2hdr_mode),
|
|
+ .mode_regs = ar0231at_1920_1088_2hdr_mode,
|
|
+ },
|
|
+ {
|
|
+ .sd_rects_items = ARRAY_SIZE(ar0231at_1920_1088_rects),
|
|
+ .sd_rects = ar0231at_1920_1088_rects,
|
|
+ .binn_hor = 1,
|
|
+ .binn_vert = 1,
|
|
+ .scale_m = 1,
|
|
+ .width = 1920,
|
|
+ .height = 1088,
|
|
+ .min_llp = 1978,
|
|
+ .min_fll = 1480,
|
|
+ .comp_items = 1,
|
|
+ .ctrl_data = &ar0231at_ctrl_data_modes[2],
|
|
+ .mode_regs_items = ARRAY_SIZE(ar0231at_1920_1088_3hdr_mode),
|
|
+ .mode_regs = ar0231at_1920_1088_3hdr_mode,
|
|
+ },
|
|
+ {
|
|
+ .sd_rects_items = ARRAY_SIZE(ar0231at_1920_1088_rects),
|
|
+ .sd_rects = ar0231at_1920_1088_rects,
|
|
+ .binn_hor = 1,
|
|
+ .binn_vert = 1,
|
|
+ .scale_m = 1,
|
|
+ .width = 1920,
|
|
+ .height = 1088,
|
|
+ .min_llp = 2246,
|
|
+ .min_fll = 1304,
|
|
+ .comp_items = 1,
|
|
+ .ctrl_data = &ar0231at_ctrl_data_modes[3],
|
|
+ .mode_regs_items = ARRAY_SIZE(ar0231at_1920_1088_4hdr_mode),
|
|
+ .mode_regs = ar0231at_1920_1088_4hdr_mode,
|
|
+ },
|
|
+ {
|
|
+ .sd_rects_items = ARRAY_SIZE(ar0231at_1920_1088_rects),
|
|
+ .sd_rects = ar0231at_1920_1088_rects,
|
|
+ .binn_hor = 1,
|
|
+ .binn_vert = 1,
|
|
+ .scale_m = 1,
|
|
+ .width = 1920,
|
|
+ .height = 1088,
|
|
+ .min_llp = 2162,
|
|
+ .min_fll = 1354,
|
|
+ .comp_items = 1,
|
|
+ .ctrl_data = &ar0231at_ctrl_data_modes[4],
|
|
+ .mode_regs_items = ARRAY_SIZE(ar0231at_1920_1088_10bit_linear_mode),
|
|
+ .mode_regs = ar0231at_1920_1088_10bit_linear_mode,
|
|
+ },
|
|
+};
|
|
+
|
|
+struct crl_csi_data_fmt ar0231at_crl_csi_data_fmt[] = {
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG12,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
+ .bits_per_pixel = 12,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG12,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_RGGB,
|
|
+ .bits_per_pixel = 12,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG12,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_BGGR,
|
|
+ .bits_per_pixel = 12,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG12,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_GBRG,
|
|
+ .bits_per_pixel = 12,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG10,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_GRBG,
|
|
+ .bits_per_pixel = 10,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG10,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_RGGB,
|
|
+ .bits_per_pixel = 10,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG10,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_BGGR,
|
|
+ .bits_per_pixel = 10,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+ {
|
|
+ .code = ICI_FORMAT_SGRBG10,
|
|
+ .pixel_order = CRL_PIXEL_ORDER_GBRG,
|
|
+ .bits_per_pixel = 10,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct crl_arithmetic_ops ar0231at_ls2_ops[] = {
|
|
+ {
|
|
+ .op = CRL_BITWISE_LSHIFT,
|
|
+ .operand.entity_val = 2,
|
|
+ }
|
|
+};
|
|
+
|
|
+/* Line length pixel */
|
|
+static struct crl_dynamic_register_access ar0231at_llp_regs[] = {
|
|
+ {
|
|
+ .address = 0x300C,
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* Frame length lines */
|
|
+static struct crl_dynamic_register_access ar0231at_fll_regs[] = {
|
|
+ {
|
|
+ .address = 0x300A,
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* Analog gain register, also used in linear(non-HDR) mode */
|
|
+static struct crl_dynamic_register_access ar0231at_ana_gain_regs[] = {
|
|
+ {
|
|
+ .address = 0x3366, /* analog gain */
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* Digital gain register */
|
|
+static struct crl_dynamic_register_access ar0231at_gl_regs[] = {
|
|
+ {
|
|
+ .address = 0x305E, /* global digital gain */
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0x07ff,
|
|
+ },
|
|
+};
|
|
+
|
|
+/*
|
|
+ * Exposure mode:
|
|
+ * 0: Linear mode
|
|
+ * 1: 2-HDR mode
|
|
+ * 2: 3-HDR mode
|
|
+ * 3: 4-HDR mode
|
|
+ */
|
|
+static struct crl_dynamic_register_access ar0231at_exposure_mode_regs[] = {
|
|
+ {
|
|
+ .address = 0x3082,
|
|
+ .len = CRL_REG_LEN_16BIT | CRL_REG_READ_AND_UPDATE,
|
|
+ .ops_items = ARRAY_SIZE(ar0231at_ls2_ops),
|
|
+ .ops = ar0231at_ls2_ops,
|
|
+ .mask = 0x000C,
|
|
+ },
|
|
+};
|
|
+
|
|
+/*
|
|
+ * Exposure Ratio in HDR mode
|
|
+ * 0x8000:
|
|
+ * Select exposure ratio mode or
|
|
+ * configure exposure time for each x-HDR individually.
|
|
+ * 0x0222:
|
|
+ * Selected exposure ratio mode and each ratio is 4x.
|
|
+ * The ratio also can be 2x, 8x, 16x
|
|
+ */
|
|
+static struct crl_dynamic_register_access ar0231at_hdr_exposure_ratio_regs[] = {
|
|
+ {
|
|
+ .address = 0x3238,
|
|
+ .len = CRL_REG_LEN_16BIT | CRL_REG_READ_AND_UPDATE,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0x8777,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* t1 exposure register, also used in linear(non-HDR) mode */
|
|
+static struct crl_dynamic_register_access ar0231at_t1expotime_regs[] = {
|
|
+ {
|
|
+ .address = 0x3012, /* coarse integration time T1 */
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* t2 exposure register, only used in HDR mode */
|
|
+static struct crl_dynamic_register_access ar0231at_t2expotime_regs[] = {
|
|
+ {
|
|
+ .address = 0x3212, /* coarse integration time T2 */
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* t3 exposure register, only used in HDR mode */
|
|
+static struct crl_dynamic_register_access ar0231at_t3expotime_regs[] = {
|
|
+ {
|
|
+ .address = 0x3216, /* coarse integration time T3 */
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+/* t4 exposure register, only used in HDR mode */
|
|
+static struct crl_dynamic_register_access ar0231at_t4expotime_regs[] = {
|
|
+ {
|
|
+ .address = 0x321A, /* coarse integration time T4 */
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct crl_dynamic_register_access ar0231at_test_pattern_regs[] = {
|
|
+ {
|
|
+ .address = 0x3070,
|
|
+ .len = CRL_REG_LEN_16BIT,
|
|
+ .ops_items = 0,
|
|
+ .ops = 0,
|
|
+ .mask = 0xffff,
|
|
+ },
|
|
+};
|
|
+
|
|
+static const char * const ar0231at_test_patterns[] = {
|
|
+ "Disabled",
|
|
+ "Solid Color",
|
|
+ "100% Vertical Color Bar",
|
|
+};
|
|
+
|
|
+struct crl_ctrl_data ar0231at_ctrls[] = {
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_BINNER,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_IDLE,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_LINK_FREQ,
|
|
+ .name = "CTRL_ID_LINK_FREQ",
|
|
+ .type = CRL_CTRL_TYPE_MENU_INT,
|
|
+ .data.int_menu.def = 0,
|
|
+ .data.int_menu.max = 0,
|
|
+ .data.int_menu.menu = 0,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_GET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_PIXEL_RATE,
|
|
+ .name = "CTRL_ID_PIXEL_RATE_PA",
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = INT_MAX,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_BINNER,
|
|
+ .op_type = CRL_CTRL_GET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_PIXEL_RATE,
|
|
+ .name = "CTRL_ID_PIXEL_RATE_CSI",
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = INT_MAX,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = 0,
|
|
+ .regs = 0,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_LINE_LENGTH_PIXELS,
|
|
+ .name = "Line Length Pixels",
|
|
+ .type = CRL_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 1920,
|
|
+ .data.std_data.max = 65535,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 1978,
|
|
+ .flags = 8,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_llp_regs),
|
|
+ .regs = ar0231at_llp_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_FRAME_LENGTH_LINES,
|
|
+ .name = "Frame Length Lines",
|
|
+ .type = CRL_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 1088,
|
|
+ .data.std_data.max = 65535,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 1480,
|
|
+ .flags = 8,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_fll_regs),
|
|
+ .regs = ar0231at_fll_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_ANALOGUE_GAIN,
|
|
+ .name = "CTRL_ID_ANALOGUE_GAIN",
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0x0000,
|
|
+ .data.std_data.max = 0xFFFF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0xAAAA,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_ana_gain_regs),
|
|
+ .regs = ar0231at_ana_gain_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_GAIN,
|
|
+ .name = "Digital Gain",
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0x0080,
|
|
+ .data.std_data.max = 0x07FF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x0080,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_gl_regs),
|
|
+ .regs = ar0231at_gl_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE,
|
|
+ .name = "CRL_CTRL_EXPOSURE_MODE",
|
|
+ .type = CRL_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = ARRAY_SIZE(ar0231at_ctrl_data_modes)-1,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x0,
|
|
+ .flags = 8,
|
|
+ .impact = CRL_IMPACTS_MODE_SELECTION,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_exposure_mode_regs),
|
|
+ .regs = ar0231at_exposure_mode_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_HDR_RATIO,
|
|
+ .name = "CRL_CTRL_EXPOSURE_HDR_RATIO",
|
|
+ .type = CRL_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0,
|
|
+ .data.std_data.max = 65535,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x0222,
|
|
+ .flags = 8,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_hdr_exposure_ratio_regs),
|
|
+ .regs = ar0231at_hdr_exposure_ratio_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE,
|
|
+ .name = "T1_COARSE_EXPOSURE_TIME",
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ .data.std_data.min = 0x0002,
|
|
+ .data.std_data.max = 0x04FF,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x0163,
|
|
+ .flags = 0,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_t1expotime_regs),
|
|
+ .regs = ar0231at_t1expotime_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE_SHS1,
|
|
+ .name = "T2_COARSE_EXPOSURE_TIME",
|
|
+ .type = CRL_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x0002,
|
|
+ .data.std_data.max = 0x0300,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x0002,
|
|
+ .flags = CRL_CTRL_FLAG_UPDATE,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_t2expotime_regs),
|
|
+ .regs = ar0231at_t2expotime_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE_SHS2,
|
|
+ .name = "T3_COARSE_EXPOSURE_TIME",
|
|
+ .type = CRL_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x0002,
|
|
+ .data.std_data.max = 0x0180,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x0002,
|
|
+ .flags = 8,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_t3expotime_regs),
|
|
+ .regs = ar0231at_t3expotime_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_EXPOSURE_SHS3,
|
|
+ .name = "T4_COARSE_EXPOSURE_TIME",
|
|
+ .type = CRL_CTRL_TYPE_CUSTOM,
|
|
+ .data.std_data.min = 0x0,
|
|
+ .data.std_data.max = 0x0500,
|
|
+ .data.std_data.step = 1,
|
|
+ .data.std_data.def = 0x0,
|
|
+ .flags = 8,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_t4expotime_regs),
|
|
+ .regs = ar0231at_t4expotime_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ .type = CRL_CTRL_TYPE_INTEGER,
|
|
+ },
|
|
+ {
|
|
+ .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY,
|
|
+ .op_type = CRL_CTRL_SET_OP,
|
|
+ .context = SENSOR_POWERED_ON,
|
|
+ .ctrl_id = ICI_EXT_SD_PARAM_ID_TEST_PATTERN,
|
|
+ .name = "CTRL_ID_TEST_PATTERN",
|
|
+ .type = CRL_CTRL_TYPE_MENU_ITEMS,
|
|
+ .data.menu_items.menu = ar0231at_test_patterns,
|
|
+ .data.menu_items.size = ARRAY_SIZE(ar0231at_test_patterns)-1,
|
|
+ .flags = 8,
|
|
+ .impact = CRL_IMPACTS_NO_IMPACT,
|
|
+ .regs_items = ARRAY_SIZE(ar0231at_test_pattern_regs),
|
|
+ .regs = ar0231at_test_pattern_regs,
|
|
+ .dep_items = 0,
|
|
+ .dep_ctrls = 0,
|
|
+ },
|
|
+};
|
|
+
|
|
+struct crl_sensor_detect_config ar0231at_sensor_detect_regset[] = {
|
|
+ {
|
|
+ .reg = { 0x3000, CRL_REG_LEN_16BIT, 0xFFFF },
|
|
+ .width = 15,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct crl_sensor_limits ar0231at_maxim_sensor_limits = {
|
|
+ .x_addr_min = 0,
|
|
+ .y_addr_min = 0,
|
|
+ .x_addr_max = 1920,
|
|
+ .y_addr_max = 1088,
|
|
+ .min_frame_length_lines = 240,
|
|
+ .max_frame_length_lines = 65535,
|
|
+ .min_line_length_pixels = 320,
|
|
+ .max_line_length_pixels = 32752,
|
|
+};
|
|
+
|
|
+struct crl_sensor_configuration ar0231at_crl_configuration = {
|
|
+ .powerup_regs_items = 0,
|
|
+ .powerup_regs = 0,
|
|
+
|
|
+ .poweroff_regs_items = 0,
|
|
+ .poweroff_regs = 0,
|
|
+
|
|
+ .power_items = 0,
|
|
+ .power_entities = 0,
|
|
+
|
|
+ .pll_config_items = ARRAY_SIZE(ar0231at_pll_configurations),
|
|
+ .pll_configs = ar0231at_pll_configurations,
|
|
+
|
|
+ .id_reg_items = ARRAY_SIZE(ar0231at_sensor_detect_regset),
|
|
+ .id_regs = ar0231at_sensor_detect_regset,
|
|
+
|
|
+ .subdev_items = ARRAY_SIZE(ar0231at_sensor_subdevs),
|
|
+ .subdevs = ar0231at_sensor_subdevs,
|
|
+
|
|
+ .modes_items = ARRAY_SIZE(ar0231at_modes),
|
|
+ .modes = ar0231at_modes,
|
|
+
|
|
+ .csi_fmts_items = ARRAY_SIZE(ar0231at_crl_csi_data_fmt),
|
|
+ .csi_fmts = ar0231at_crl_csi_data_fmt,
|
|
+
|
|
+ .ctrl_items = ARRAY_SIZE(ar0231at_ctrls),
|
|
+ .ctrl_bank = ar0231at_ctrls,
|
|
+
|
|
+ .streamon_regs_items = 0,
|
|
+ .streamon_regs = 0,
|
|
+ .streamoff_regs_items = 0,
|
|
+ .streamoff_regs = 0,
|
|
+
|
|
+ .sensor_limits = &ar0231at_maxim_sensor_limits,
|
|
+
|
|
+};
|
|
+
|
|
+#endif /* __CRLMODULE_AR0231AT_CONFIGURATION_H_ */
|
|
diff --git a/drivers/media/i2c/crlmodule-lite/crlmodule-data.c b/drivers/media/i2c/crlmodule-lite/crlmodule-data.c
|
|
index 000982f89a2e..846d81254ba0 100644
|
|
--- a/drivers/media/i2c/crlmodule-lite/crlmodule-data.c
|
|
+++ b/drivers/media/i2c/crlmodule-lite/crlmodule-data.c
|
|
@@ -9,6 +9,7 @@
|
|
#include "crl_adv7481_eval_configuration.h"
|
|
#include "crl_magna_configuration_ti964.h"
|
|
#include "crl_ov10635_configuration.h"
|
|
+#include "crl_ar0231at_configuration.h"
|
|
|
|
static const struct crlmodule_sensors supported_sensors[] = {
|
|
{ "ADV7481 CVBS", "adv7481_cvbs", &adv7481_cvbs_crl_configuration },
|
|
@@ -19,6 +20,7 @@ static const struct crlmodule_sensors supported_sensors[] = {
|
|
{ "i2c-ADV7481A:00", "adv7481_hdmi", &adv7481_hdmi_crl_configuration },
|
|
{ "i2c-ADV7481B:00", "adv7481_cvbs", &adv7481_cvbs_crl_configuration },
|
|
{ "OV10635", "ov10635", &ov10635_crl_configuration },
|
|
+ { "AR0231AT", "ar0231at", &ar0231at_crl_configuration },
|
|
};
|
|
|
|
/*
|
|
diff --git a/drivers/media/i2c/ici/Kconfig b/drivers/media/i2c/ici/Kconfig
|
|
index db4fd7f79b22..dd967ac80d8f 100644
|
|
--- a/drivers/media/i2c/ici/Kconfig
|
|
+++ b/drivers/media/i2c/ici/Kconfig
|
|
@@ -8,6 +8,12 @@ config VIDEO_TI964_ICI
|
|
---help---
|
|
This is a driver for TI964 camera for ICI.
|
|
|
|
+config VIDEO_MAX9286_ICI
|
|
+ tristate "MAX9286 driver support"
|
|
+ depends on I2C && VIDEO_INTEL_ICI
|
|
+ ---help---
|
|
+ This is a driver for MAX9286 camera for ICI.
|
|
+
|
|
endmenu
|
|
|
|
endif
|
|
diff --git a/drivers/media/i2c/ici/Makefile b/drivers/media/i2c/ici/Makefile
|
|
index 232f0cc76313..4450c5effb94 100644
|
|
--- a/drivers/media/i2c/ici/Makefile
|
|
+++ b/drivers/media/i2c/ici/Makefile
|
|
@@ -1,2 +1,3 @@
|
|
# SPDX-License-Identifier: GPL-2.0
|
|
obj-$(CONFIG_VIDEO_TI964_ICI) += ti964_ici.o
|
|
+obj-$(CONFIG_VIDEO_MAX9286_ICI) += max9286_ici.o
|
|
diff --git a/drivers/media/i2c/ici/max9286_ici.c b/drivers/media/i2c/ici/max9286_ici.c
|
|
new file mode 100644
|
|
index 000000000000..8fc998ba8b18
|
|
--- /dev/null
|
|
+++ b/drivers/media/i2c/ici/max9286_ici.c
|
|
@@ -0,0 +1,1103 @@
|
|
+/* SPDX-LIcense_Identifier: GPL-2.0 */
|
|
+/* Copyright (C) 2018 Intel Corporation */
|
|
+
|
|
+#include <linux/device.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/slab.h>
|
|
+#include <linux/wait.h>
|
|
+#include <linux/platform_device.h>
|
|
+#include <linux/delay.h>
|
|
+
|
|
+#include <media/ici.h>
|
|
+#include <media/max9286.h>
|
|
+#include <media/crlmodule-lite.h>
|
|
+
|
|
+#include "../max9286-reg-settings.h"
|
|
+
|
|
+struct max9286_subdev {
|
|
+ struct ici_ext_subdev *sd;
|
|
+ unsigned short rx_port;
|
|
+ unsigned short fsin_gpio;
|
|
+ unsigned short phy_i2c_addr;
|
|
+ unsigned short alias_i2c_addr;
|
|
+ char sd_name[ICI_MAX_NODE_NAME];
|
|
+};
|
|
+
|
|
+struct max9286 {
|
|
+ struct ici_ext_subdev ici_sd;
|
|
+ struct ici_ext_subdev_register reg;
|
|
+ struct max9286_pdata *pdata;
|
|
+ struct crlmodule_lite_platform_data subdev_pdata[NR_OF_MAX_SINK_PADS];
|
|
+ unsigned char sensor_present;
|
|
+ unsigned int total_sensor_num;
|
|
+ unsigned int nsources;
|
|
+ unsigned int nsinks;
|
|
+ unsigned int npads;
|
|
+ unsigned int nstreams;
|
|
+ const char *name;
|
|
+ struct max9286_subdev sub_devs[NR_OF_MAX_SINK_PADS];
|
|
+ struct ici_framefmt *ffmts[NR_OF_MAX_PADS];
|
|
+
|
|
+ struct rect *crop;
|
|
+ struct rect *compose;
|
|
+ struct {
|
|
+ unsigned int *stream_id;
|
|
+ } *stream; /* stream enable/disable status, indexed by pad */
|
|
+ struct {
|
|
+ unsigned int sink;
|
|
+ unsigned int source;
|
|
+ int flags;
|
|
+ } *route; /* pad level info, indexed by stream */
|
|
+
|
|
+ struct regmap *regmap8;
|
|
+ struct mutex max_mutex;
|
|
+ int (*create_link)(
|
|
+ struct ici_isys_node *src,
|
|
+ u16 src_pad,
|
|
+ struct ici_isys_node *sink,
|
|
+ u16 sink_pad,
|
|
+ u32 flags);
|
|
+};
|
|
+
|
|
+#define to_max_9286(_sd) container_of(_sd, struct max9286, ici_sd)
|
|
+#define to_ici_ext_subdev(_node) container_of(_node, struct ici_ext_subdev, node)
|
|
+
|
|
+/*
|
|
+ * Order matters.
|
|
+ *
|
|
+ * 1. Bits-per-pixel, descending.
|
|
+ * 2. Bits-per-pixel compressed, descending.
|
|
+ * 3. Pixel order, same as in pixel_order_str. Formats for all four pixel
|
|
+ * orders must be defined.
|
|
+ */
|
|
+static const struct max9286_csi_data_format max_csi_data_formats[] = {
|
|
+ { ICI_FORMAT_YUYV, 16, 16, PIXEL_ORDER_GBRG, 0x1e },
|
|
+ { ICI_FORMAT_UYVY, 16, 16, PIXEL_ORDER_GBRG, 0x1e },
|
|
+ { ICI_FORMAT_SGRBG12, 12, 12, PIXEL_ORDER_GRBG, 0x2c },
|
|
+ { ICI_FORMAT_SRGGB12, 12, 12, PIXEL_ORDER_RGGB, 0x2c },
|
|
+ { ICI_FORMAT_SBGGR12, 12, 12, PIXEL_ORDER_BGGR, 0x2c },
|
|
+ { ICI_FORMAT_SGBRG12, 12, 12, PIXEL_ORDER_GBRG, 0x2c },
|
|
+ { ICI_FORMAT_SGRBG10, 10, 10, PIXEL_ORDER_GRBG, 0x2b },
|
|
+ { ICI_FORMAT_SRGGB10, 10, 10, PIXEL_ORDER_RGGB, 0x2b },
|
|
+ { ICI_FORMAT_SBGGR10, 10, 10, PIXEL_ORDER_BGGR, 0x2b },
|
|
+ { ICI_FORMAT_SGBRG10, 10, 10, PIXEL_ORDER_GBRG, 0x2b },
|
|
+ { ICI_FORMAT_SGRBG8, 8, 8, PIXEL_ORDER_GRBG, 0x2a },
|
|
+ { ICI_FORMAT_SRGGB8, 8, 8, PIXEL_ORDER_RGGB, 0x2a },
|
|
+ { ICI_FORMAT_SBGGR8, 8, 8, PIXEL_ORDER_BGGR, 0x2a },
|
|
+ { ICI_FORMAT_SGBRG8, 8, 8, PIXEL_ORDER_GBRG, 0x2a },
|
|
+};
|
|
+
|
|
+static struct regmap_config max9286_reg_config8 = {
|
|
+ .reg_bits = 8,
|
|
+ .val_bits = 8,
|
|
+};
|
|
+
|
|
+/* Serializer register write */
|
|
+static int max96705_write_register(struct max9286 *max,
|
|
+ unsigned int offset, u8 reg, u8 val)
|
|
+{
|
|
+ int ret;
|
|
+ int retry, timeout = 10;
|
|
+ struct i2c_client *client = max->ici_sd.client;
|
|
+
|
|
+ client->addr = S_ADDR_MAX96705 + offset;
|
|
+ for (retry = 0; retry < timeout; retry++) {
|
|
+ ret = i2c_smbus_write_byte_data(client, reg, val);
|
|
+ if (val < 0)
|
|
+ usleep_range(5000, 6000);
|
|
+ else
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ client->addr = DS_ADDR_MAX9286;
|
|
+ if (retry >= timeout) {
|
|
+ pr_err("%s:write reg failed: reg=%2x\n", __func__, reg);
|
|
+ return -EREMOTEIO;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* Serializer register read */
|
|
+static int
|
|
+max96705_read_register(struct max9286 *max, unsigned int i, u8 reg)
|
|
+{
|
|
+ int val;
|
|
+ int retry, timeout = 10;
|
|
+ struct i2c_client *client = max->ici_sd.client;
|
|
+
|
|
+ client->addr = S_ADDR_MAX96705 + i;
|
|
+ for (retry = 0; retry < timeout; retry++) {
|
|
+ val = i2c_smbus_read_byte_data(client, reg);
|
|
+ if (val >= 0)
|
|
+ break;
|
|
+ usleep_range(5000, 6000);
|
|
+ }
|
|
+
|
|
+ client->addr = DS_ADDR_MAX9286;
|
|
+ if (retry >= timeout) {
|
|
+ pr_err("%s:read reg failed: reg=%2x\n", __func__, reg);
|
|
+ return -EREMOTEIO;
|
|
+ }
|
|
+
|
|
+ return val;
|
|
+}
|
|
+
|
|
+/* Validate csi_data_format */
|
|
+static const struct max9286_csi_data_format *
|
|
+max9286_validate_csi_data_format(u32 code)
|
|
+{
|
|
+ unsigned int i;
|
|
+
|
|
+ for (i = 0; i < ARRAY_SIZE(max_csi_data_formats); i++) {
|
|
+ if (max_csi_data_formats[i].code == code)
|
|
+ return &max_csi_data_formats[i];
|
|
+ }
|
|
+
|
|
+ return &max_csi_data_formats[0];
|
|
+}
|
|
+
|
|
+/* Initialize image sensors and set stream on registers */
|
|
+static int max9286_set_stream(
|
|
+ struct ici_isys_node *node,
|
|
+ void *ip,
|
|
+ int enable)
|
|
+{
|
|
+ struct ici_ext_subdev *subsubdev = node->sd;
|
|
+ struct ici_ext_subdev *subdev = i2c_get_clientdata(subsubdev->client);
|
|
+ struct max9286 *max = to_max_9286(subdev);
|
|
+
|
|
+ int i, rval, j;
|
|
+ unsigned int val;
|
|
+ u8 slval = 0xE0;
|
|
+ u8 dtval = 0xF7;
|
|
+ const struct max9286_register_write *max9286_byte_order_settings;
|
|
+
|
|
+ pr_info("MAX9286 set stream. enable = %d\n", enable);
|
|
+ /* Disable I2C ACK */
|
|
+ rval = regmap_write(max->regmap8, DS_I2CLOCACK, 0xB6);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to disable I2C ACK!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ for (i = 0; i < NR_OF_MAX_SINK_PADS; i++) {
|
|
+ if (((0x01 << (i)) & max->sensor_present) == 0)
|
|
+ continue;
|
|
+
|
|
+ if (strncmp(node->name, max->sub_devs[i].sd_name, ICI_MAX_NODE_NAME))
|
|
+ continue;
|
|
+
|
|
+ if (enable) {
|
|
+ /*
|
|
+ * Enable CSI-2 lanes D0, D1, D2, D3
|
|
+ * Enable CSI-2 DBL (Double Input Mode)
|
|
+ * Enable GMSL DBL for RAWx2
|
|
+ * Enable RAW10/RAW12 data type
|
|
+ */
|
|
+ u8 bpp;
|
|
+ const struct max9286_csi_data_format *csi_format =
|
|
+ max9286_validate_csi_data_format(max->ffmts[i]->pixelformat);
|
|
+
|
|
+ bpp = csi_format->compressed;
|
|
+
|
|
+ if (bpp == 10) {
|
|
+ dtval = 0xF6;
|
|
+ max9286_byte_order_settings =
|
|
+ &max9286_byte_order_settings_10bit[0];
|
|
+ } else if (bpp == 12) {
|
|
+ dtval = 0xF7;
|
|
+ max9286_byte_order_settings =
|
|
+ &max9286_byte_order_settings_12bit[0];
|
|
+ } else {
|
|
+ pr_err("Only support RAW10/12, current bpp is %d!\n", bpp);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ rval = regmap_write(max->regmap8, DS_CSI_DBL_DT, dtval);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to set data type!\n");
|
|
+ return rval;
|
|
+ }
|
|
+
|
|
+ for (j = 0; j < bpp * 2; j++) {
|
|
+ rval = max96705_write_register(max,
|
|
+ S_ADDR_MAX96705_BROADCAST - S_ADDR_MAX96705,
|
|
+ (max9286_byte_order_settings + j)->reg,
|
|
+ (max9286_byte_order_settings + j)->val);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to set max9286 byte order\n");
|
|
+ return rval;
|
|
+ }
|
|
+ }
|
|
+ usleep_range(2000, 3000);
|
|
+ }
|
|
+
|
|
+ /* Enable link */
|
|
+ slval |= (0x0F & (1 << i));
|
|
+ rval = regmap_write(max->regmap8, DS_LINK_ENABLE, slval);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to enable GMSL links!\n");
|
|
+ return rval;
|
|
+ }
|
|
+
|
|
+ rval = regmap_write(max->regmap8, DS_ATUO_MASK_LINK, 0x30);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to write 0x69\n");
|
|
+ return rval;
|
|
+ }
|
|
+ }
|
|
+#if 0
|
|
+ /* Enable I2C ACK */
|
|
+ rval = regmap_write(max->regmap8, DS_I2CLOCACK, 0x36);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to enable I2C ACK!\n");
|
|
+ return rval;
|
|
+ }
|
|
+#endif
|
|
+ /* Check if valid PCLK is available for the links */
|
|
+ for (i = 1; i <= NR_OF_MAX_SINK_PADS; i++) {
|
|
+ if (((0x01 << (i - 1)) & max->sensor_present) == 0)
|
|
+ continue;
|
|
+
|
|
+ val = max96705_read_register(max, i, S_INPUT_STATUS);
|
|
+ if ((val != -EREMOTEIO) && (val & 0x01))
|
|
+ pr_info("Valid PCLK detected for link %d\n", i);
|
|
+ else if (val != -EREMOTEIO)
|
|
+ pr_info("Failed to read PCLK reg for link %d\n", i);
|
|
+ }
|
|
+
|
|
+ /* Set preemphasis settings for all serializers (set to 3.3dB)*/
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_CMLLVL_PREEMP, 0xAA);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ /* Set VSYNC Delay */
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_SYNC_GEN_CONFIG, 0x21);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_VS_DLY_2, 0x06);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_VS_DLY_1, 0xD8);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_VS_H_2, 0x26);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_VS_H_1, 0x00);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_VS_H_0, 0x00);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_DBL_ALIGN_TO, 0xC4);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ /* Enable link equalizers */
|
|
+ rval = regmap_write(max->regmap8, DS_ENEQ, 0x0F);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to automatically detect serial data rate!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ usleep_range(5000, 6000);
|
|
+ rval = regmap_write(max->regmap8, DS_HS_VS, 0x91);
|
|
+
|
|
+ /* Enable serial links and desable configuration */
|
|
+ max96705_write_register(max, S_ADDR_MAX96705_BROADCAST -
|
|
+ S_ADDR_MAX96705, S_MAIN_CTL, 0x83);
|
|
+ /* Wait for more than 2 Frames time from each sensor */
|
|
+ usleep_range(100000, 101000);
|
|
+
|
|
+ /*
|
|
+ * Poll frame synchronization bit of deserializer
|
|
+ * All the cameras should work in SYNC mode
|
|
+ * MAX9286 sends a pulse to each camera, then each camera sends out
|
|
+ * one frame. The VSYNC for each camera should appear in almost same
|
|
+ * time for the deserializer to lock FSYNC
|
|
+ */
|
|
+ rval = regmap_read(max->regmap8, DS_FSYNC_LOCKED, &val);
|
|
+ if (rval) {
|
|
+ pr_info("Frame SYNC not locked!\n");
|
|
+ return rval;
|
|
+ } else if (val & (0x01 << 6))
|
|
+ pr_info("Deserializer Frame SYNC locked\n");
|
|
+
|
|
+ /*
|
|
+ * Enable/set bit[7] of DS_CSI_VC_CTL register for VC operation
|
|
+ * Set VC according to the link number
|
|
+ * Enable CSI-2 output
|
|
+ */
|
|
+ if (!enable) {
|
|
+ rval = regmap_write(max->regmap8, DS_CSI_VC_CTL, 0x93);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to disable CSI output!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ } else {
|
|
+ rval = regmap_write(max->regmap8, DS_CSI_VC_CTL, 0x9B);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to enable CSI output!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* callback for VIDIOC_SUBDEV_G_FMT ioctl handler code */
|
|
+static int max9286_get_format(struct ici_isys_node *node,
|
|
+ struct ici_pad_framefmt *fmt)
|
|
+{
|
|
+ struct ici_ext_subdev *subsubdev = node->sd;
|
|
+ struct ici_ext_subdev *subdev = i2c_get_clientdata(subsubdev->client);
|
|
+ struct max9286 *max = to_max_9286(subdev);
|
|
+ int i;
|
|
+
|
|
+
|
|
+ mutex_lock(&max->max_mutex);
|
|
+
|
|
+ for (i = 0; i < NR_OF_MAX_SINK_PADS; i++) {
|
|
+
|
|
+ if (strncmp(node->name, max->sub_devs[i].sd_name, ICI_MAX_NODE_NAME))
|
|
+ continue;
|
|
+
|
|
+
|
|
+ fmt->ffmt.width = max->ffmts[i]->width;
|
|
+ fmt->ffmt.height = max->ffmts[i]->height;
|
|
+ fmt->ffmt.pixelformat = max->ffmts[i]->pixelformat;
|
|
+ fmt->ffmt.field = max->ffmts[i]->field;
|
|
+ fmt->ffmt.colorspace = max->ffmts[i]->colorspace;
|
|
+ fmt->ffmt.flags = max->ffmts[i]->flags;
|
|
+
|
|
+ mutex_unlock(&max->max_mutex);
|
|
+
|
|
+ pr_info("framefmt: width: %d, height: %d, code: 0x%x.\n",
|
|
+ fmt->ffmt.width, fmt->ffmt.height, fmt->ffmt.pixelformat);
|
|
+
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ mutex_unlock(&max->max_mutex);
|
|
+
|
|
+ pr_err("max9286_get_format: unknown node name \n");
|
|
+
|
|
+ return -1;
|
|
+}
|
|
+
|
|
+/* Enumerate media bus formats available at a given sub-device pad */
|
|
+static int max9286_enum_mbus_code(struct ici_isys_node *node,
|
|
+ struct ici_pad_supported_format_desc *psfd)
|
|
+{
|
|
+// struct ici_ext_subdev *subsubdev = node->sd;
|
|
+// struct ici_ext_subdev *subdev = i2c_get_clientdata(subsubdev->client);
|
|
+
|
|
+ pr_err(" TBD !\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int max9286_get_param(struct ici_ext_sd_param *param)
|
|
+{
|
|
+
|
|
+ if (param->id == ICI_EXT_SD_PARAM_ID_LINK_FREQ) {
|
|
+ param->val = 87750000;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int max9286_set_param(struct ici_ext_sd_param *param)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int max9286_get_menu_item(struct ici_ext_sd_param *param, u32 idx)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int max9286_set_power(struct ici_isys_node *node, int on)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* callback for VIDIOC_SUBDEV_S_FMT ioctl handler code */
|
|
+static int max9286_set_format(struct ici_isys_node *node,
|
|
+ struct ici_pad_framefmt *fmt)
|
|
+{
|
|
+ struct ici_ext_subdev *subsubdev = node->sd;
|
|
+ struct ici_ext_subdev *subdev = i2c_get_clientdata(subsubdev->client);
|
|
+ struct max9286 *max = to_max_9286(subdev);
|
|
+ const struct max9286_csi_data_format *csi_format;
|
|
+ int i;
|
|
+
|
|
+ csi_format = max9286_validate_csi_data_format(fmt->ffmt.colorspace);
|
|
+
|
|
+ mutex_lock(&max->max_mutex);
|
|
+
|
|
+ for (i = 0; i < NR_OF_MAX_SINK_PADS; i++) {
|
|
+
|
|
+ if (strncmp(node->name, max->sub_devs[i].sd_name, ICI_MAX_NODE_NAME))
|
|
+ continue;
|
|
+
|
|
+
|
|
+ max->ffmts[i]->width = fmt->ffmt.width;
|
|
+ max->ffmts[i]->height = fmt->ffmt.height;
|
|
+ max->ffmts[i]->pixelformat = fmt->ffmt.pixelformat;
|
|
+ max->ffmts[i]->field = fmt->ffmt.field;
|
|
+ max->ffmts[i]->colorspace = fmt->ffmt.colorspace;
|
|
+ max->ffmts[i]->flags = fmt->ffmt.flags;
|
|
+
|
|
+ mutex_unlock(&max->max_mutex);
|
|
+
|
|
+ pr_info("framefmt: width: %d, height: %d, code: 0x%x.\n",
|
|
+ fmt->ffmt.width, fmt->ffmt.height, fmt->ffmt.pixelformat);
|
|
+
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ mutex_unlock(&max->max_mutex);
|
|
+
|
|
+ pr_err("max9286_set_format: unknown node name\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int max9286_set_selection(struct ici_isys_node *node, struct ici_pad_selection *ps)
|
|
+{
|
|
+// TODO place holder
|
|
+ pr_err(" TBD!!! \n");
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int max9286_get_selection(struct ici_isys_node *node, struct ici_pad_selection *ps)
|
|
+{
|
|
+// TODO place holder
|
|
+ pr_err(" TBD!!! \n");
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int init_ext_sd(struct i2c_client *client, struct max9286_subdev *max_sd, int idx)
|
|
+{
|
|
+ int rval;
|
|
+ struct ici_ext_subdev *subdev = i2c_get_clientdata(client);;
|
|
+ struct max9286 *max = to_max_9286(subdev);
|
|
+ char name[ICI_MAX_NODE_NAME];
|
|
+
|
|
+ snprintf(name, sizeof(name), "MAX9286 %d", idx);
|
|
+
|
|
+ strncpy(max->sub_devs[idx].sd_name, name, sizeof(name));
|
|
+
|
|
+ max_sd->sd->client = client;
|
|
+ max_sd->sd->num_pads = 2;
|
|
+ max_sd->sd->pads[0].pad_id = 0;
|
|
+ max_sd->sd->pads[0].flags = ICI_PAD_FLAGS_SINK;
|
|
+ max_sd->sd->pads[1].pad_id = 1;
|
|
+ max_sd->sd->pads[1].flags = ICI_PAD_FLAGS_SOURCE;
|
|
+// TODO
|
|
+// sd->src_pad = ssd->source_pad;
|
|
+// below fnctions invoked by csi2 fe code
|
|
+ max_sd->sd->set_param = max9286_set_param; // meant to execute CTRL-IDs/CIDs
|
|
+ max_sd->sd->get_param = max9286_get_param; // meant to execute CTRLIDs/CIDs
|
|
+ max_sd->sd->get_menu_item = max9286_get_menu_item; // get LINK FREQ
|
|
+ if (max->reg.setup_node) {
|
|
+ rval = max->reg.setup_node(max->reg.ipu_data,
|
|
+ max_sd->sd, name);
|
|
+ if (rval)
|
|
+ return rval;
|
|
+ } else {
|
|
+ pr_err("node not registered\n");
|
|
+ }
|
|
+
|
|
+// below invoked by stream code
|
|
+ max_sd->sd->node.node_set_power = max9286_set_power;
|
|
+ max_sd->sd->node.node_set_streaming = max9286_set_stream;
|
|
+// below invoked by pipeline-device code
|
|
+ max_sd->sd->node.node_get_pad_supported_format =
|
|
+ max9286_enum_mbus_code; //needs modification
|
|
+ max_sd->sd->node.node_set_pad_ffmt = max9286_set_format;
|
|
+ max_sd->sd->node.node_get_pad_ffmt = max9286_get_format;
|
|
+ max_sd->sd->node.node_set_pad_sel = max9286_set_selection;
|
|
+ max_sd->sd->node.node_get_pad_sel = max9286_get_selection;
|
|
+
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int create_link(struct ici_isys_node *src_node,
|
|
+ u16 srcpad,
|
|
+ struct ici_isys_node *sink_node,
|
|
+ u16 sinkpad,
|
|
+ u32 flag)
|
|
+{
|
|
+ struct ici_ext_subdev *sd, *ssd;
|
|
+ struct max9286 *max;
|
|
+ struct max9286_subdev *subdev;
|
|
+ int i, ret;
|
|
+ if (!src_node || !sink_node)
|
|
+ return -EINVAL;
|
|
+
|
|
+ sd = to_ici_ext_subdev(src_node);
|
|
+ if (!sd)
|
|
+ return -EINVAL;
|
|
+
|
|
+ max = to_max_9286(sd);
|
|
+ if (!max)
|
|
+ return -EINVAL;
|
|
+
|
|
+ for (i = 0; i < NR_OF_MAX_SINK_PADS; i++) {
|
|
+ subdev = &max->sub_devs[i];
|
|
+ if (!subdev)
|
|
+ continue;
|
|
+ ssd = subdev->sd;
|
|
+ ret = max->create_link(&ssd->node,
|
|
+ 1,
|
|
+ sink_node,
|
|
+ sinkpad,
|
|
+ 0);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/*
|
|
+ * called when this subdev is registered.
|
|
+ */
|
|
+static int max9286_registered(struct ici_ext_subdev_register *reg)
|
|
+{
|
|
+ struct ici_ext_subdev *subdev = reg->sd;
|
|
+ struct i2c_client *client = subdev->client;
|
|
+ struct ici_isys *isys = reg->ipu_data;
|
|
+ struct max9286 *max = to_max_9286(subdev);
|
|
+ struct max9286_subdev *sd, *prev_sd = NULL;
|
|
+ int i, k, rval, num, nsinks;
|
|
+
|
|
+
|
|
+ num = max->pdata->subdev_num;
|
|
+ nsinks = max->nsinks;
|
|
+
|
|
+ max->reg = *reg;
|
|
+ max->create_link = reg->create_link;
|
|
+
|
|
+ subdev->get_param = max9286_get_param;
|
|
+ subdev->set_param = max9286_set_param;
|
|
+ subdev->get_menu_item = max9286_get_menu_item;
|
|
+
|
|
+ for (i = 0, k = 0; (i < num) && (k < nsinks); i++, k++) {
|
|
+ struct max9286_subdev_i2c_info *info =
|
|
+ &max->pdata->subdev_info[i];
|
|
+ struct crlmodule_lite_platform_data *pdata =
|
|
+ (struct crlmodule_lite_platform_data *)
|
|
+ info->board_info.platform_data;
|
|
+
|
|
+ if (i >= nsinks)
|
|
+ break;
|
|
+
|
|
+ /* Spin the sensor subdev name suffix */
|
|
+// pdata->suffix = info->suffix;
|
|
+
|
|
+ memcpy(&max->subdev_pdata[i], pdata, sizeof(*pdata));
|
|
+
|
|
+ max->subdev_pdata[i].suffix = info->suffix;
|
|
+ info->board_info.platform_data = &max->subdev_pdata[i];
|
|
+
|
|
+ struct i2c_client *client2;
|
|
+ struct ici_ext_subdev *sensor_sd;
|
|
+ struct ici_ext_subdev_register sd_register = {0};
|
|
+
|
|
+ request_module(I2C_MODULE_PREFIX "%s", info->board_info.type);
|
|
+
|
|
+ client2 = i2c_new_device(client->adapter, &info->board_info);
|
|
+
|
|
+ if (client2 == NULL || client2->dev.driver == NULL) {
|
|
+ pr_err("@%s, No new i2c device\n", __func__);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ /* Get the clientdata set by the sensor driver */
|
|
+ sensor_sd = i2c_get_clientdata(client2);
|
|
+ if (!sensor_sd)
|
|
+ pr_err("@%s, Failed to get client data\n", __func__);
|
|
+
|
|
+ sd_register.ipu_data = isys;
|
|
+ sd_register.sd = sensor_sd;
|
|
+ sd_register.setup_node = reg->setup_node;
|
|
+ sd_register.create_link = reg->create_link;
|
|
+ rval = sensor_sd->do_register(&sd_register);
|
|
+ if (rval) {
|
|
+ pr_err("@%s, Failed to register external subdev\n", __func__);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+
|
|
+
|
|
+ max->sub_devs[k].sd = devm_kzalloc(&client->dev, sizeof(struct ici_ext_subdev), GFP_KERNEL);
|
|
+ if (!max->sub_devs[k].sd) {
|
|
+ pr_err("can't create MAX9286 subdev %d\n", i);
|
|
+ continue;
|
|
+ }
|
|
+// max->sub_devs[k].rx_port = info->rx_port;
|
|
+// max->sub_devs[k].phy_i2c_addr = info->phy_i2c_addr;
|
|
+ max->sub_devs[k].alias_i2c_addr = info->board_info.addr;
|
|
+
|
|
+ sd = &max->sub_devs[k];
|
|
+ rval = init_ext_sd(max->ici_sd.client, sd, k);
|
|
+ if (rval)
|
|
+ return rval;
|
|
+
|
|
+ rval = sd_register.create_link(&sensor_sd->node,
|
|
+ sensor_sd->src_pad,
|
|
+ &sd->sd->node, 0, 0);
|
|
+ if (rval) {
|
|
+ pr_err("@%s, error creating link\n", __func__);
|
|
+ return rval;
|
|
+ }
|
|
+
|
|
+ prev_sd = sd;
|
|
+ }
|
|
+
|
|
+ /* Replace existing create_link address with MAX9286 create_link implementation
|
|
+ to create link between MAX9286 node and CSI2 node */
|
|
+ reg->create_link = create_link;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void max9286_unregistered(struct ici_ext_subdev *subdev)
|
|
+{
|
|
+ pr_debug("%s DO NOTHING ?? \n", __func__);
|
|
+}
|
|
+
|
|
+static const s64 max9286_op_sys_clock[] = { 87750000, };
|
|
+/* Registers MAX9286 sub-devices (Image sensors) */
|
|
+static int max9286_register_subdev(struct max9286 *max, struct i2c_client *client)
|
|
+{
|
|
+ int i;
|
|
+
|
|
+ max->ici_sd.client = client;
|
|
+ max->ici_sd.do_register = max9286_registered;
|
|
+ max->ici_sd.do_unregister = max9286_unregistered;
|
|
+
|
|
+ i2c_set_clientdata(client, &max->ici_sd);
|
|
+
|
|
+ for (i = 0; i < NR_OF_MAX_SINK_PADS; i++) {
|
|
+ max->ffmts[i]->width = 1920;
|
|
+ max->ffmts[i]->height = 1088;
|
|
+ max->ffmts[i]->pixelformat = ICI_FORMAT_SGRBG10;
|
|
+ max->ffmts[i]->field = ICI_FIELD_NONE;
|
|
+ snprintf(max->sub_devs[i].sd_name, sizeof(max->sub_devs[i].sd_name),
|
|
+ "MAX9286 %d", i);
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/*
|
|
+ * Get the output link order
|
|
+ * By default:
|
|
+ * bits[7:6] 11: Link 3 is 4th in the CSI-2 output order
|
|
+ * bits[5:4] 10: Link 2 is 3rd in the CSI-2 output order
|
|
+ * bits[3:2] 01: Link 1 is 2nd in the CSI-2 output order
|
|
+ * bits[1:0] 00: Link 0 is 1st in the CSI-2 output order
|
|
+ */
|
|
+static u8 get_output_link_order(struct max9286 *max)
|
|
+{
|
|
+ u8 val = 0xE4, i;
|
|
+ u8 order_config[14][3] = {
|
|
+ {1, 8, 0x27},
|
|
+ {1, 4, 0xC6},
|
|
+ {1, 2, 0xE1},
|
|
+ {1, 1, 0xE4},
|
|
+ {2, 0xC, 0x4E},
|
|
+ {2, 0xA, 0x72},
|
|
+ {2, 0x9, 0x78},
|
|
+ {2, 0x6, 0xD2},
|
|
+ {2, 0x5, 0xD8},
|
|
+ {2, 0x3, 0xE4},
|
|
+ {3, 0xE, 0x93},
|
|
+ {3, 0xD, 0x9C},
|
|
+ {3, 0xB, 0xB4},
|
|
+ {3, 0x7, 0xE4},
|
|
+ };
|
|
+
|
|
+ if (max->total_sensor_num < 4) {
|
|
+ for (i = 0; i < 14; i++) {
|
|
+ if ((max->total_sensor_num == order_config[i][0])
|
|
+ && (max->sensor_present == order_config[i][1]))
|
|
+ return order_config[i][2];
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* sensor_num = 4 will return 0xE4 */
|
|
+ return val;
|
|
+}
|
|
+
|
|
+/* MAX9286 initial setup and Reverse channel setup */
|
|
+static int max9286_init(struct max9286 *max, struct i2c_client *client)
|
|
+{
|
|
+ int i, rval;
|
|
+ unsigned int val, lval;
|
|
+ u8 mval, slval, tmval;
|
|
+
|
|
+ usleep_range(10000, 11000);
|
|
+
|
|
+ rval = regmap_read(max->regmap8, DS_MAX9286_DEVID, &val);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to read device ID of MAX9286!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ pr_info("MAX9286 device ID: 0x%X\n", val);
|
|
+
|
|
+ rval = regmap_write(max->regmap8, DS_CSI_VC_CTL, 0x93);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to disable CSI output!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ /* All the links are working in Legacy reverse control-channel mode */
|
|
+ /* Enable Custom Reverse Channel and First Pulse Length */
|
|
+ rval = regmap_write(max->regmap8, DS_ENCRC_FPL, 0x4F);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to disable PRBS test!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ /*
|
|
+ * 2ms of delay is required after any analog change to reverse control
|
|
+ * channel for bus timeout and I2C state machine to settle from any
|
|
+ * glitches
|
|
+ */
|
|
+ usleep_range(2000, 3000);
|
|
+ /* First pulse length rise time changed from 300ns to 200ns */
|
|
+ rval = regmap_write(max->regmap8, DS_FPL_RT, 0x1E);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to disable PRBS test!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ usleep_range(2000, 3000);
|
|
+
|
|
+ /* Enable configuration links */
|
|
+ max96705_write_register(max, 0, S_MAIN_CTL, 0x43);
|
|
+ usleep_range(5000, 6000);
|
|
+
|
|
+ /*
|
|
+ * Enable high threshold for reverse channel input buffer
|
|
+ * This increases immunity to power supply noise when the
|
|
+ * coaxial link is used for power as well as signal
|
|
+ */
|
|
+ max96705_write_register(max, 0, S_RSVD_8, 0x01);
|
|
+ /* Enable change of reverse control parameters */
|
|
+
|
|
+ max96705_write_register(max, 0, S_RSVD_97, 0x5F);
|
|
+
|
|
+ /* Wait 2ms after any change to reverse control channel */
|
|
+ usleep_range(2000, 3000);
|
|
+
|
|
+ /* Increase reverse amplitude from 100mV to 170mV to compensate for
|
|
+ * higher threshold
|
|
+ */
|
|
+ rval = regmap_write(max->regmap8, DS_FPL_RT, 0x19);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to disable PRBS test!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ usleep_range(2000, 3000);
|
|
+
|
|
+ /*
|
|
+ * Enable CSI-2 lanes D0, D1, D2, D3
|
|
+ * Enable CSI-2 DBL (Double Input Mode)
|
|
+ * Enable GMSL DBL for RAWx2
|
|
+ * Enable RAW12 data type by default
|
|
+ */
|
|
+ rval = regmap_write(max->regmap8, DS_CSI_DBL_DT, 0xF7); //RAW12
|
|
+ if (rval) {
|
|
+ pr_err("Failed to set data type!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ usleep_range(2000, 3000);
|
|
+
|
|
+ /* Enable Frame sync Auto-mode for row/column reset on frame sync
|
|
+ * sensors
|
|
+ */
|
|
+ rval = regmap_write(max->regmap8, DS_FSYNCMODE, 0x00);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to set frame sync mode!\n");
|
|
+ return rval;
|
|
+ }
|
|
+ usleep_range(2000, 3000);
|
|
+ rval = regmap_write(max->regmap8, DS_OVERLAP_WIN_LOW, 0x00);
|
|
+ rval = regmap_write(max->regmap8, DS_OVERLAP_WIN_HIGH, 0x00);
|
|
+
|
|
+ rval = regmap_write(max->regmap8, DS_FSYNC_PERIOD_LOW, 0x55);
|
|
+ rval = regmap_write(max->regmap8, DS_FSYNC_PERIOD_MIDDLE, 0xc2);
|
|
+ rval = regmap_write(max->regmap8, DS_FSYNC_PERIOD_HIGH, 0x2C);
|
|
+
|
|
+ rval = regmap_write(max->regmap8, DS_HIGHIMM, 0x06);
|
|
+
|
|
+ /*
|
|
+ * Enable DBL
|
|
+ * Edge select: Rising Edge
|
|
+ * Enable HS/VS encoding
|
|
+ */
|
|
+ max96705_write_register(max, 0, S_CONFIG, 0xD4);
|
|
+ usleep_range(2000, 3000);
|
|
+
|
|
+ for (i = 0; i < ARRAY_SIZE(max9286_byte_order_settings_12bit); i++) {
|
|
+ rval = max96705_write_register(max, 0,
|
|
+ max9286_byte_order_settings_12bit[i].reg,
|
|
+ max9286_byte_order_settings_12bit[i].val);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to set max9286 byte order\n");
|
|
+ return rval;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* Detect video links */
|
|
+ rval = regmap_read(max->regmap8, DS_CONFIGL_VIDEOL_DET, &lval);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to read register 0x49!\n");
|
|
+ return rval;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * Check on which links the sensors are connected
|
|
+ * And also check total number of sensors connected to the deserializer
|
|
+ */
|
|
+ max->sensor_present = ((lval >> 4) & 0xF) | (lval & 0xF);
|
|
+
|
|
+ for (i = 0; i < NR_OF_MAX_STREAMS; i++) {
|
|
+ if (max->sensor_present & (0x1 << i)) {
|
|
+ pr_info("Sensor present on deserializer link %d\n", i);
|
|
+ max->total_sensor_num += 1;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ pr_info("total sensor present = %d", max->total_sensor_num);
|
|
+ pr_info("sensor present on links = %d", max->sensor_present);
|
|
+
|
|
+ if (!max->total_sensor_num) {
|
|
+ pr_err("No sensors connected!\n");
|
|
+ } else {
|
|
+ pr_info("Total number of sensors connected = %d\n",
|
|
+ max->total_sensor_num);
|
|
+ }
|
|
+
|
|
+ slval = get_output_link_order(max);
|
|
+
|
|
+ /* Set link output order */
|
|
+ rval = regmap_write(max->regmap8, DS_LINK_OUTORD, slval);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to set Link output order!\n");
|
|
+ return rval;
|
|
+ }
|
|
+
|
|
+ slval = 0xE0 | max->sensor_present;
|
|
+
|
|
+ mval = 0;
|
|
+ tmval = 0;
|
|
+ /*
|
|
+ * Setup each serializer individually and their respective I2C slave
|
|
+ * address changed to a unique value by enabling one reverse channel
|
|
+ * at a time via deserializer's DS_FWDCCEN_REVCCEN control register.
|
|
+ * Also create broadcast slave address for MAX96705 serializer.
|
|
+ * After this stage, i2cdetect on I2C-ADAPTER should display the
|
|
+ * below devices
|
|
+ * 10: Sensor address
|
|
+ * 11, 12, 13, 14: Sensors alias addresses
|
|
+ * 41, 42, 43, 44: Serializers alias addresses
|
|
+ * 45: Serializer's broadcast address
|
|
+ * 48: Deserializer's address
|
|
+ */
|
|
+
|
|
+ for (i = 1; i <= NR_OF_MAX_SINK_PADS; i++) {
|
|
+ /* Setup the link when the sensor is connected to the link */
|
|
+ if (((0x1 << (i - 1)) & max->sensor_present) == 0)
|
|
+ continue;
|
|
+
|
|
+ /* Enable only one reverse channel at a time */
|
|
+ mval = (0x11 << (i - 1));
|
|
+ tmval |= (0x11 << (i - 1));
|
|
+ rval = regmap_write(max->regmap8, DS_FWDCCEN_REVCCEN, mval);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to enable channel for %d!\n", i);
|
|
+ return rval;
|
|
+ }
|
|
+ /* Wait 2ms after enabling reverse channel */
|
|
+ usleep_range(2000, 3000);
|
|
+
|
|
+ /* Change Serializer slave address */
|
|
+ max96705_write_register(max, 0, S_SERADDR,
|
|
+ (S_ADDR_MAX96705 + i) << 1);
|
|
+ /* Unique link 'i' image sensor slave address */
|
|
+ max96705_write_register(max, i, S_I2C_SOURCE_IS,
|
|
+ (ADDR_AR0231AT_SENSOR + i) << 1);
|
|
+ /* Link 'i' image sensor slave address */
|
|
+ max96705_write_register(max, i, S_I2C_DST_IS,
|
|
+ ADDR_AR0231AT_SENSOR << 1);
|
|
+ /* Serializer broadcast address */
|
|
+ max96705_write_register(max, i, S_I2C_SOURCE_SER,
|
|
+ S_ADDR_MAX96705_BROADCAST << 1);
|
|
+ /* Link 'i' serializer address */
|
|
+ max96705_write_register(max, i, S_I2C_DST_SER,
|
|
+ (S_ADDR_MAX96705 + i) << 1);
|
|
+ }
|
|
+
|
|
+ /* Enable I2c reverse channels */
|
|
+ rval = regmap_write(max->regmap8, DS_FWDCCEN_REVCCEN, tmval);
|
|
+ if (rval) {
|
|
+ pr_err("Failed to enable channel for %d!\n", i);
|
|
+ return rval;
|
|
+ }
|
|
+ usleep_range(2000, 3000);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* Unbind the MAX9286 device driver from the I2C client */
|
|
+static int max9286_remove(struct i2c_client *client)
|
|
+{
|
|
+ struct ici_ext_subdev *subdev = i2c_get_clientdata(client);
|
|
+ struct max9286 *max = to_max_9286(subdev);
|
|
+ int i;
|
|
+
|
|
+ mutex_destroy(&max->max_mutex);
|
|
+
|
|
+ for (i = 0; i < NR_OF_MAX_SINK_PADS; i++) {
|
|
+ max->sub_devs[i].sd = NULL;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* Called by I2C probe */
|
|
+static int max9286_probe(struct i2c_client *client,
|
|
+ const struct i2c_device_id *devid)
|
|
+{
|
|
+ struct max9286 *max;
|
|
+ int i = 0;
|
|
+ int rval = 0;
|
|
+
|
|
+ if (client->dev.platform_data == NULL)
|
|
+ return -ENODEV;
|
|
+
|
|
+ dev_err(&client->dev, "MAX9286 probe!\n");
|
|
+ max = devm_kzalloc(&client->dev, sizeof(*max), GFP_KERNEL);
|
|
+ if (!max)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ max->pdata = client->dev.platform_data;
|
|
+
|
|
+ max->nsources = NR_OF_MAX_SOURCE_PADS;
|
|
+ max->nsinks = NR_OF_MAX_SINK_PADS;
|
|
+ max->npads = NR_OF_MAX_PADS;
|
|
+ max->nstreams = NR_OF_MAX_STREAMS;
|
|
+
|
|
+ max->crop = devm_kcalloc(&client->dev, max->npads,
|
|
+ sizeof(struct ici_rect), GFP_KERNEL);
|
|
+ max->compose = devm_kcalloc(&client->dev, max->npads,
|
|
+ sizeof(struct ici_rect), GFP_KERNEL);
|
|
+ max->route = devm_kcalloc(&client->dev, max->nstreams,
|
|
+ sizeof(*max->route), GFP_KERNEL);
|
|
+ max->stream = devm_kcalloc(&client->dev, max->npads,
|
|
+ sizeof(*max->stream), GFP_KERNEL);
|
|
+
|
|
+ if (!max->crop || !max->compose || !max->route || !max->stream)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ for (i = 0; i < max->npads; i++) {
|
|
+ max->ffmts[i] =
|
|
+ devm_kcalloc(&client->dev, max->nstreams,
|
|
+ sizeof(struct ici_framefmt), GFP_KERNEL);
|
|
+ if (!max->ffmts[i])
|
|
+ return -ENOMEM;
|
|
+
|
|
+ max->stream[i].stream_id =
|
|
+ devm_kcalloc(&client->dev, max->nsinks,
|
|
+ sizeof(int), GFP_KERNEL);
|
|
+ if (!max->stream[i].stream_id)
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < max->nstreams; i++) {
|
|
+ max->route[i].sink = i;
|
|
+ max->route[i].source = MAX_PAD_SOURCE;
|
|
+ max->route[i].flags = 0;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < max->nsinks; i++) {
|
|
+ max->stream[i].stream_id[0] = i;
|
|
+ max->stream[MAX_PAD_SOURCE].stream_id[i] = i;
|
|
+ }
|
|
+
|
|
+ max->regmap8 = devm_regmap_init_i2c(client, &max9286_reg_config8);
|
|
+ if (IS_ERR(max->regmap8)) {
|
|
+ dev_err(&client->dev, "Failed to init regmap8!\n");
|
|
+ return -EIO;
|
|
+ }
|
|
+
|
|
+ mutex_init(&max->max_mutex);
|
|
+
|
|
+ rval = max9286_register_subdev(max, client);
|
|
+ if (rval) {
|
|
+ dev_err(&client->dev,
|
|
+ "Failed to register MAX9286 subdevice!\n");
|
|
+ goto error_mutex_destroy;
|
|
+ }
|
|
+
|
|
+ rval = max9286_init(max, client);
|
|
+ if (rval) {
|
|
+ dev_err(&client->dev, "Failed to initialise MAX9286!\n");
|
|
+ goto error_media_entity;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+
|
|
+error_media_entity:
|
|
+error_mutex_destroy:
|
|
+ mutex_destroy(&max->max_mutex);
|
|
+
|
|
+ return rval;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+static int max9286_resume(struct device *dev)
|
|
+{
|
|
+ struct i2c_client *client = to_i2c_client(dev);
|
|
+ struct ici_ext_subdev *subdev = i2c_get_clientdata(client);
|
|
+ struct max9286 *max = to_max_9286(subdev);
|
|
+
|
|
+ return max9286_init(max, client);
|
|
+}
|
|
+#else
|
|
+#define max9286_resume NULL
|
|
+#endif /* CONFIG_PM */
|
|
+
|
|
+static const struct i2c_device_id max9286_id_table[] = {
|
|
+ { MAX9286_NAME, 0 },
|
|
+ {},
|
|
+};
|
|
+
|
|
+static const struct dev_pm_ops max9286_pm_ops = {
|
|
+ .resume = max9286_resume,
|
|
+};
|
|
+
|
|
+static struct i2c_driver max9286_i2c_driver = {
|
|
+ .driver = {
|
|
+ .name = MAX9286_NAME,
|
|
+ .pm = &max9286_pm_ops,
|
|
+ },
|
|
+ .probe = max9286_probe,
|
|
+ .remove = max9286_remove,
|
|
+ .id_table = max9286_id_table,
|
|
+};
|
|
+
|
|
+module_i2c_driver(max9286_i2c_driver);
|
|
+
|
|
+MODULE_AUTHOR("Karthik Gopalakrishnan <karthik.l.gopalakrishnan@intel.com>");
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_DESCRIPTION("Maxim96705 serializer and Maxim9286 deserializer driver");
|
|
diff --git a/drivers/media/platform/intel/ipu4-ici-bxt-p-pdata.c b/drivers/media/platform/intel/ipu4-ici-bxt-p-pdata.c
|
|
index f6bf4992670d..df0c9619d9d1 100644
|
|
--- a/drivers/media/platform/intel/ipu4-ici-bxt-p-pdata.c
|
|
+++ b/drivers/media/platform/intel/ipu4-ici-bxt-p-pdata.c
|
|
@@ -12,6 +12,7 @@
|
|
#include <media/ipu-isys.h>
|
|
#include <media/crlmodule-lite.h>
|
|
#include <media/ti964.h>
|
|
+#include <media/max9286.h>
|
|
#include "ipu.h"
|
|
|
|
#define GPIO_BASE 422
|
|
@@ -336,6 +337,93 @@ static struct ipu_isys_subdev_info ti964_sd_2 = {
|
|
};
|
|
#endif
|
|
|
|
+#ifdef CONFIG_INTEL_IPU4_AR0231AT
|
|
+#define AR0231AT_LANES 4
|
|
+#define AR0231ATA_I2C_ADDRESS 0x11
|
|
+#define AR0231ATB_I2C_ADDRESS 0x12
|
|
+#define AR0231ATC_I2C_ADDRESS 0x13
|
|
+#define AR0231ATD_I2C_ADDRESS 0x14
|
|
+
|
|
+static struct crlmodule_lite_platform_data ar0231at_pdata = {
|
|
+ .lanes = AR0231AT_LANES,
|
|
+ .ext_clk = 27000000,
|
|
+ .op_sys_clock = (uint64_t[]){ 87750000 },
|
|
+ .module_name = "AR0231AT",
|
|
+};
|
|
+#endif
|
|
+
|
|
+#if IS_ENABLED(CONFIG_VIDEO_MAX9286_ICI)
|
|
+#define DS_MAX9286_LANES 4
|
|
+#define DS_MAX9286_I2C_ADAPTER 4
|
|
+#define DS_MAX9286_I2C_ADDRESS 0x48
|
|
+
|
|
+static struct ipu_isys_csi2_config max9286_csi2_cfg = {
|
|
+ .nlanes = DS_MAX9286_LANES,
|
|
+ .port = 4,
|
|
+};
|
|
+
|
|
+static struct max9286_subdev_i2c_info max9286_subdevs[] = {
|
|
+#ifdef CONFIG_INTEL_IPU4_AR0231AT
|
|
+ {
|
|
+ .board_info = {
|
|
+ .type = CRLMODULE_LITE_NAME,
|
|
+ .addr = AR0231ATA_I2C_ADDRESS,
|
|
+ .platform_data = &ar0231at_pdata,
|
|
+ },
|
|
+ .i2c_adapter_id = DS_MAX9286_I2C_ADAPTER,
|
|
+ .suffix = 'a',
|
|
+ },
|
|
+ {
|
|
+ .board_info = {
|
|
+ .type = CRLMODULE_LITE_NAME,
|
|
+ .addr = AR0231ATB_I2C_ADDRESS,
|
|
+ .platform_data = &ar0231at_pdata,
|
|
+ },
|
|
+ .i2c_adapter_id = DS_MAX9286_I2C_ADAPTER,
|
|
+ .suffix = 'b',
|
|
+ },
|
|
+ {
|
|
+ .board_info = {
|
|
+ .type = CRLMODULE_LITE_NAME,
|
|
+ .addr = AR0231ATC_I2C_ADDRESS,
|
|
+ .platform_data = &ar0231at_pdata,
|
|
+ },
|
|
+ .i2c_adapter_id = DS_MAX9286_I2C_ADAPTER,
|
|
+ .suffix = 'c',
|
|
+ },
|
|
+ {
|
|
+ .board_info = {
|
|
+ .type = CRLMODULE_LITE_NAME,
|
|
+ .addr = AR0231ATD_I2C_ADDRESS,
|
|
+ .platform_data = &ar0231at_pdata,
|
|
+ },
|
|
+ .i2c_adapter_id = DS_MAX9286_I2C_ADAPTER,
|
|
+ .suffix = 'd',
|
|
+ },
|
|
+#endif
|
|
+};
|
|
+
|
|
+
|
|
+static struct max9286_pdata max9286_pdata = {
|
|
+ .subdev_info = max9286_subdevs,
|
|
+ .subdev_num = ARRAY_SIZE(max9286_subdevs),
|
|
+ .reset_gpio = GPIO_BASE + 63,
|
|
+ .suffix = 'a',
|
|
+};
|
|
+
|
|
+static struct ipu_isys_subdev_info max9286_sd = {
|
|
+ .csi2 = &max9286_csi2_cfg,
|
|
+ .i2c = {
|
|
+ .board_info = {
|
|
+ .type = "max9286",
|
|
+ .addr = DS_MAX9286_I2C_ADDRESS,
|
|
+ .platform_data = &max9286_pdata,
|
|
+ },
|
|
+ .i2c_adapter_id = DS_MAX9286_I2C_ADAPTER,
|
|
+ }
|
|
+};
|
|
+#endif
|
|
+
|
|
/*
|
|
* Map buttress output sensor clocks to sensors -
|
|
* this should be coming from ACPI
|
|
@@ -364,7 +452,10 @@ static struct ipu_isys_subdev_pdata pdata = {
|
|
&ti964_sd_2,
|
|
#endif
|
|
#ifdef CONFIG_INTEL_IPU4_MAGNA_TI964
|
|
- &magna_ti964_crl_sd,
|
|
+ &magna_ti964_crl_sd,
|
|
+#endif
|
|
+#if IS_ENABLED(CONFIG_VIDEO_MAX9286_ICI)
|
|
+ &max9286_sd,
|
|
#endif
|
|
NULL,
|
|
},
|
|
diff --git a/include/media/ici.h b/include/media/ici.h
|
|
index bf5a542dafb3..353a5a7efb72 100644
|
|
--- a/include/media/ici.h
|
|
+++ b/include/media/ici.h
|
|
@@ -81,6 +81,11 @@ enum ici_ext_sd_param_id {
|
|
ICI_EXT_SD_PARAM_ID_THERMAL_DATA,
|
|
ICI_EXT_SD_PARAM_ID_MIPI_LANES,
|
|
ICI_EXT_SD_PARAM_ID_WDR_MODE,
|
|
+ ICI_EXT_SD_PARAM_ID_EXPOSURE_MODE,
|
|
+ ICI_EXT_SD_PARAM_ID_HDR_RATIO,
|
|
+ ICI_EXT_SD_PARAM_ID_EXPOSURE_SHS1,
|
|
+ ICI_EXT_SD_PARAM_ID_EXPOSURE_SHS2,
|
|
+ ICI_EXT_SD_PARAM_ID_EXPOSURE_SHS3,
|
|
};
|
|
|
|
enum ici_ext_sd_param_type {
|
|
--
|
|
https://clearlinux.org
|
|
|