105 lines
5.4 KiB
Diff
105 lines
5.4 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Yang Zhonghua <zhonghuax.yang@intel.com>
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Date: Fri, 28 Dec 2018 17:41:30 +0800
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Subject: [PATCH] media: intel-ipu4: [ICI] Fix cvbs image quality issues
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Update i2c power up initialization in crl_adv7481_configuration.h
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Change-Id: I912d9942283cdce4f13a656a46fdd326d1e8ce2d
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Tracked-On: OAM-72018
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Tracked-On: OAM-71884
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Tracked-On: OAM-73743
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Tracked-On: OAM-73701
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Tracked-On: OAM-73660
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Signed-off-by: Jin, Jia <jiax.jin@intel.com>
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---
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.../crl_adv7481_cvbs_configuration.h | 72 ++++++++++++-------
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1 file changed, 45 insertions(+), 27 deletions(-)
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diff --git a/drivers/media/i2c/crlmodule-lite/crl_adv7481_cvbs_configuration.h b/drivers/media/i2c/crlmodule-lite/crl_adv7481_cvbs_configuration.h
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index 5ea1f7c01f19..b077c5cb09c4 100644
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--- a/drivers/media/i2c/crlmodule-lite/crl_adv7481_cvbs_configuration.h
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+++ b/drivers/media/i2c/crlmodule-lite/crl_adv7481_cvbs_configuration.h
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@@ -9,33 +9,51 @@
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#include "crlmodule-sensor-ds.h"
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static struct crl_register_write_rep adv7481_cvbs_powerup_regset[] = {
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- {0x0E, CRL_REG_LEN_08BIT, 0xFF, 0xE0}, //LLC/PIX/AUD/SPI PINS TRISTATED
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- {0x0F, CRL_REG_LEN_08BIT, 0x00, 0xF2}, //Exit Power Down Mode
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- {0x52, CRL_REG_LEN_08BIT, 0xCD, 0xF2}, //ADI Required Write
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- {0x00, CRL_REG_LEN_08BIT, 0x00, 0xF2}, //INSEL = CVBS in on Ain 1
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- {0x0E, CRL_REG_LEN_08BIT, 0x80, 0xF2}, //ADI Required Write
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- {0x9C, CRL_REG_LEN_08BIT, 0x00, 0xF2}, //ADI Required Write
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- {0x9C, CRL_REG_LEN_08BIT, 0xFF, 0xF2}, //ADI Required Write
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- {0x0E, CRL_REG_LEN_08BIT, 0x00, 0xF2}, //ADI Required Write
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- {0x80, CRL_REG_LEN_08BIT, 0x51, 0xF2}, //ADI Required Write
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- {0x81, CRL_REG_LEN_08BIT, 0x51, 0xF2}, //ADI Required Write
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- {0x82, CRL_REG_LEN_08BIT, 0x68, 0xF2}, //ADI Required Write
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- {0x03, CRL_REG_LEN_08BIT, 0x42, 0xF2}, //Tri-S Output Drivers, PwrDwn 656 pads
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- {0x04, CRL_REG_LEN_08BIT, 0x07, 0xF2}, //Power-up INTRQ pad, & Enable SFL
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- {0x13, CRL_REG_LEN_08BIT, 0x00, 0xF2}, //ADI Required Write
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- {0x17, CRL_REG_LEN_08BIT, 0x41, 0xF2}, //Select SH1
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- {0x31, CRL_REG_LEN_08BIT, 0x12, 0xF2}, //ADI Required Write
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- {0x10, CRL_REG_LEN_08BIT, 0xC0, 0xE0}, //Enable 1-Lane MIPI Tx, enable pixel output and route SD through Pixel port
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- {0x00, CRL_REG_LEN_08BIT, 0x81, 0x90}, //Enable 1-lane MIPI
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- {0x00, CRL_REG_LEN_08BIT, 0xA1, 0x90}, //Set Auto DPHY Timing
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- {0xF0, CRL_REG_LEN_08BIT, 0x00, 0x94}, //ADI Required Write
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- {0xD2, CRL_REG_LEN_08BIT, 0x40, 0x90}, //ADI Required Write
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- {0xC4, CRL_REG_LEN_08BIT, 0x0A, 0x90}, //ADI Required Write
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- {0x71, CRL_REG_LEN_08BIT, 0x33, 0x90}, //ADI Required Write
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- {0x72, CRL_REG_LEN_08BIT, 0x11, 0x90}, //ADI Required Write
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- {0xF0, CRL_REG_LEN_08BIT, 0x00, 0x90}, //i2c_dphy_pwdn - 1'b0
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- {0x31, CRL_REG_LEN_08BIT, 0x82, 0x90}, //ADI Required Write
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- {0x1E, CRL_REG_LEN_08BIT, 0xC0, 0x90}, //ADI Required Write
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+ {0x0E, CRL_REG_LEN_08BIT, 0xFF, 0xE0}, /* LLC/PIX/AUD/
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+ SPI PINS TRISTATED */
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+ {0x0F, CRL_REG_LEN_08BIT, 0x00, 0xF2}, /* Exit Power Down Mode */
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+ {0x52, CRL_REG_LEN_08BIT, 0xC0, 0xF2}, /* ADI Required Write */
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+ {0x00, CRL_REG_LEN_08BIT, 0x0E, 0xF2}, /* INSEL = CVBS in on Ain 1 */
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+ {0x0E, CRL_REG_LEN_08BIT, 0x80, 0xF2}, /* ADI Required Write */
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+ {0x9C, CRL_REG_LEN_08BIT, 0x00, 0xF2}, /* ADI Required Write */
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+ {0x9C, CRL_REG_LEN_08BIT, 0xFF, 0xF2}, /* ADI Required Write */
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+ {0x0E, CRL_REG_LEN_08BIT, 0x00, 0xF2}, /* ADI Required Write */
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+ {0x5A, CRL_REG_LEN_08BIT, 0x90, 0xF2}, /* ADI Required Write */
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+ {0x60, CRL_REG_LEN_08BIT, 0xA0, 0xF2}, /* ADI Required Write */
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+ {0x00, CRL_REG_LEN_DELAY, 0x19, 0x00}, /* Delay 25*/
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+ {0x60, CRL_REG_LEN_08BIT, 0xB0, 0xF2}, /* ADI Required Write */
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+ {0x5F, CRL_REG_LEN_08BIT, 0xA8, 0xF2},
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+ {0x0E, CRL_REG_LEN_08BIT, 0x80, 0xF2}, /* ADI Required Write */
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+ {0xB6, CRL_REG_LEN_08BIT, 0x08, 0xF2}, /* ADI Required Write */
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+ {0xC0, CRL_REG_LEN_08BIT, 0xA0, 0xF2}, /* ADI Required Write */
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+ {0xD9, CRL_REG_LEN_08BIT, 0x44, 0xF2},
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+ {0x0E, CRL_REG_LEN_08BIT, 0x40, 0xF2},
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+ {0xE0, CRL_REG_LEN_08BIT, 0x01, 0xF2}, /* Fast Lock enable*/
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+ {0x0E, CRL_REG_LEN_08BIT, 0x00, 0xF2}, /* ADI Required Write */
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+ {0x80, CRL_REG_LEN_08BIT, 0x51, 0xF2}, /* ADI Required Write */
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+ {0x81, CRL_REG_LEN_08BIT, 0x51, 0xF2}, /* ADI Required Write */
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+ {0x82, CRL_REG_LEN_08BIT, 0x68, 0xF2}, /* ADI Required Write */
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+ {0x03, CRL_REG_LEN_08BIT, 0x42, 0xF2}, /* Tri-S Output Drivers,
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+ PwrDwn 656 pads */
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+ {0x04, CRL_REG_LEN_08BIT, 0x07, 0xF2}, /* Power-up INTRQ pad,
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+ & Enable SFL */
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+ {0x13, CRL_REG_LEN_08BIT, 0x00, 0xF2}, /* ADI Required Write */
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+ {0x17, CRL_REG_LEN_08BIT, 0x41, 0xF2}, /* Select SH1 */
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+ {0x31, CRL_REG_LEN_08BIT, 0x12, 0xF2}, /* ADI Required Write */
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+ {0x10, CRL_REG_LEN_08BIT | CRL_REG_READ_AND_UPDATE, 0x70, 0xE0, 0x70 },
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+ /* Enable 1-Lane MIPI Tx,
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+ enable pixel output and route
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+ SD through Pixel port */
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+ {0x00, CRL_REG_LEN_08BIT, 0x81, 0x90}, /* Enable 1-lane MIPI */
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+ {0x00, CRL_REG_LEN_08BIT, 0xA1, 0x90}, /* Set Auto DPHY Timing */
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+ {0xF0, CRL_REG_LEN_08BIT, 0x00, 0x94}, /* ADI Required Write */
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+ {0xD2, CRL_REG_LEN_08BIT, 0x40, 0x90}, /* ADI Required Write */
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+ {0xC4, CRL_REG_LEN_08BIT, 0x0A, 0x90}, /* ADI Required Write */
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+ {0x71, CRL_REG_LEN_08BIT, 0x33, 0x90}, /* ADI Required Write */
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+ {0x72, CRL_REG_LEN_08BIT, 0x11, 0x90}, /* ADI Required Write */
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+ {0xF0, CRL_REG_LEN_08BIT, 0x00, 0x90}, /* i2c_dphy_pwdn - 1'b0 */
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+ {0x31, CRL_REG_LEN_08BIT, 0x82, 0x90}, /* ADI Required Write */
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+ {0x1E, CRL_REG_LEN_08BIT, 0xC0, 0x90}, /* ADI Required Write */
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};
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--
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https://clearlinux.org
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