173 lines
5.0 KiB
Diff
173 lines
5.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Ping Gao <ping.a.gao@intel.com>
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Date: Thu, 31 Aug 2017 10:45:05 +0800
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Subject: [PATCH] drm/i915/gvt: Introduce non-context MMIO check routines
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Guest conformance check can be implemented by verifying whether the
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non-context MMIOs have the same values with host snapshot.
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This patch introduced some routines, snapshot the host registers values
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and compare when with corresponding vregs by walking the non-context
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MMIO list.
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Signed-off-by: Ping Gao <ping.a.gao@intel.com>
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Reviewed-by: Kevin Tian
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Reviewed-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-on:
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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v2: rebase 4.19:
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1. reuse engine_mmio_list->mmio in commit cd7e61b93d06 drm/i915/gvt:
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init mmio by lri command in vgpu inhibit context
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2. split part of code to 2b5955ee506d - drm/i915/gvt: Forbid command to
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access non-context registers
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Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
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---
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drivers/gpu/drm/i915/gvt/gvt.h | 6 ++
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drivers/gpu/drm/i915/gvt/handlers.c | 9 +++
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drivers/gpu/drm/i915/gvt/mmio_context.c | 76 +++++++++++++++++++++++++
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3 files changed, 91 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
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index 68cc50f75803..708d690b8c4f 100644
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--- a/drivers/gpu/drm/i915/gvt/gvt.h
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+++ b/drivers/gpu/drm/i915/gvt/gvt.h
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@@ -289,10 +289,16 @@ struct intel_gvt_mmio {
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struct gvt_mmio_block *mmio_block;
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unsigned int num_mmio_block;
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+ void *mmio_host_cache;
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+ bool host_cache_initialized;
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DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
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unsigned long num_tracked_mmio;
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};
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+/* Macro for easily access host engine mmio cached register */
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+#define gvt_host_reg(gvt, reg) \
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+ (*(u32 *)(gvt->mmio.mmio_host_cache + reg)) \
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+
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struct intel_gvt_firmware {
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void *cfg_space;
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void *mmio;
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index ce25433c6d77..f923ca71ab8e 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -3435,6 +3435,9 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
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vfree(gvt->mmio.mmio_attribute);
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gvt->mmio.mmio_attribute = NULL;
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+
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+ vfree(gvt->mmio.mmio_host_cache);
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+ gvt->mmio.mmio_host_cache = NULL;
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}
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/* Special MMIO blocks. */
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@@ -3469,6 +3472,12 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
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if (!gvt->mmio.mmio_attribute)
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return -ENOMEM;
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+ gvt->mmio.mmio_host_cache = vzalloc(info->mmio_size);
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+ if (!gvt->mmio.mmio_host_cache) {
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+ vfree(gvt->mmio.mmio_attribute);
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+ return -ENOMEM;
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+ }
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+
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ret = init_generic_mmio_info(gvt);
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if (ret)
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goto err;
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diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
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index 0221e87f34db..99b01ab60dc3 100644
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--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
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+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
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@@ -567,6 +567,82 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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}
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+#define MMIO_COMPARE(vgpu, reg, mask) ({ \
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+ int ret; \
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+ u32 value = vgpu_vreg(vgpu, reg); \
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+ u32 host_value = gvt_host_reg(vgpu->gvt, reg); \
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+ \
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+ if (mask) { \
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+ value &= mask; \
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+ host_value &= mask; \
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+ } \
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+ if (host_value == value) { \
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+ ret = 0; \
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+ } else { \
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+ gvt_err("vgpu%d unconformance mmio 0x%x:0x%x,0x%x\n", \
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+ vgpu->id, reg, \
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+ vgpu_vreg(vgpu, reg), \
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+ gvt_host_reg(vgpu->gvt, reg)); \
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+ ret = -EINVAL; \
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+ } \
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+ ret; \
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+ })
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+
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+static int noncontext_mmio_compare(struct intel_vgpu *vgpu, int ring_id)
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+{
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+ struct engine_mmio *mmio, *mmio_list;
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+
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+ mmio_list = vgpu->gvt->engine_mmio_list.mmio;
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+
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+ for (mmio = mmio_list; i915_mmio_reg_valid(mmio->reg); mmio++) {
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+ if (mmio->ring_id != ring_id || mmio->in_context)
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+ continue;
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+
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+ if (MMIO_COMPARE(vgpu, mmio->reg.reg, mmio->mask))
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static void get_host_mmio_snapshot(struct intel_gvt *gvt)
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+{
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+ struct drm_i915_private *dev_priv = gvt->dev_priv;
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+ struct engine_mmio *mmio, *mmio_list;
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+
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+ mmio_list = gvt->engine_mmio_list.mmio;
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+
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+ if (!gvt->mmio.host_cache_initialized) {
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+ /* Snapshot all the non-context MMIOs */
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+ for (mmio = mmio_list; i915_mmio_reg_valid(mmio->reg); mmio++) {
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+ if (mmio->in_context)
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+ continue;
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+
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+ gvt_host_reg(gvt, mmio->reg.reg) =
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+ I915_READ_FW(mmio->reg);
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+ if (mmio->mask)
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+ gvt_host_reg(gvt, mmio->reg.reg) &= mmio->mask;
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+ }
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+ gvt->mmio.host_cache_initialized = true;
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+ }
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+}
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+
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+int intel_gvt_vgpu_conformance_check(struct intel_vgpu *vgpu, int ring_id)
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+{
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+ int ret;
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+
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+ get_host_mmio_snapshot(vgpu->gvt);
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+
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+ ret = noncontext_mmio_compare(vgpu, ring_id);
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+ if (ret)
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+ goto err;
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+
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+ return 0;
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+err:
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+ return ret;
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+}
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+
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+
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/**
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* intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
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* @gvt: GVT device
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--
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https://clearlinux.org
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