79 lines
3.0 KiB
Diff
79 lines
3.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Zhipeng Gong <zhipeng.gong@intel.com>
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Date: Thu, 20 Sep 2018 13:10:45 +0800
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Subject: [PATCH] drm/i915/gvt: use plane size for fb decoder
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Current fb decoder returns pipe src size to user space,
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while ggtt surface sharing only show primary plane framebuffer.
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When plane fb size is smaller than pipe size, some garbages
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are showed.
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This patch change fb decoder to use plane size to avoid
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those garbages.
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v2:
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- align size to PAGE_SIZE
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Tracked-On: projectacrn/acrn-hypervisor#1301
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Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
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Reviewed-by: He, Min <min.he@intel.com>
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---
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drivers/gpu/drm/i915/gvt/fb_decoder.c | 9 +++++----
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drivers/gpu/drm/i915/gvt/fb_decoder.h | 4 ++++
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drivers/gpu/drm/i915/i915_gem_gvtbuffer.c | 3 +--
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3 files changed, 10 insertions(+), 6 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
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index 28f02cb6c835..f8ce268286bb 100644
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--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
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+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
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@@ -267,11 +267,12 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
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(_PRI_PLANE_STRIDE_MASK >> 6) :
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_PRI_PLANE_STRIDE_MASK, plane->bpp);
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- plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
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- _PIPE_H_SRCSZ_SHIFT;
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+ plane->width = vgpu_vreg_t(vgpu, PLANE_SIZE(pipe, PLANE_PRIMARY))&
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+ _PLANE_SIZE_WIDTH_MASK;
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+
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plane->width += 1;
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- plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
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- _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
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+ plane->height = (vgpu_vreg_t(vgpu, PLANE_SIZE(pipe, PLANE_PRIMARY)) &
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+ _PLANE_SIZE_HEIGHT_MASK) >> _PLANE_SIZE_HEIGHT_SHIFT;
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plane->height += 1; /* raw height is one minus the real value */
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val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
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diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h
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index a202f9f6e81a..51626759534b 100644
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--- a/drivers/gpu/drm/i915/gvt/fb_decoder.h
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+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h
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@@ -50,6 +50,10 @@
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#define _PRI_PLANE_Y_OFF_SHIFT 16
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#define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT)
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+#define _PLANE_SIZE_HEIGHT_SHIFT 16
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+#define _PLANE_SIZE_HEIGHT_MASK (0xfff << _PLANE_SIZE_HEIGHT_SHIFT)
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+#define _PLANE_SIZE_WIDTH_MASK 0x1fff
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+
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#define _CURSOR_MODE 0x3f
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#define _CURSOR_ALPHA_FORCE_SHIFT 8
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#define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT)
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diff --git a/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c b/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c
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index fe723099788d..f482eceb5c7f 100644
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--- a/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c
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+++ b/drivers/gpu/drm/i915/i915_gem_gvtbuffer.c
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@@ -195,8 +195,7 @@ static int gvt_decode_information(struct drm_device *dev,
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return -EINVAL;
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}
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- args->size = (((args->width * args->height * args->bpp) / 8) +
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- (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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+ args->size = ALIGN(args->stride * args->height, PAGE_SIZE) >> PAGE_SHIFT;
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if (args->start & (PAGE_SIZE - 1)) {
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DRM_DEBUG_DRIVER("GVT_GEM: Not aligned fb start address: "
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--
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https://clearlinux.org
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