147 lines
4.3 KiB
Diff
147 lines
4.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Zhipeng Gong <zhipeng.gong@intel.com>
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Date: Fri, 14 Sep 2018 16:10:21 +0800
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Subject: [PATCH] drm/i915/gvt: notify global gtt update through g2v
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This patch extends g2v notification to notify host GVT-g of
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ggtt update from guest, including ggtt_insert_entries and
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ggtt_clear_range. This patch also add one new pvmmio level
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to control ggtt update.
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This patch is needed for both uos and sos.
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v2:
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- calculate num_entries from gtt_entries.
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v3:
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- pass cache_level to GVT-g
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- consolidate the same code into a function.
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Tracked-On: projectacrn/acrn-hypervisor#994
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Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
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Reviewed-by: He, Min <min.he@intel.com>
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---
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drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++++++++++++++
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drivers/gpu/drm/i915/i915_pvinfo.h | 12 ++++++++-
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2 files changed, 51 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
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index cb940a583c14..d6baa2d63a58 100644
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--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
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+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
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@@ -2513,6 +2513,17 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
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writeq(pte, addr);
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}
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+static void vgpu_ggtt_insert(struct drm_i915_private *dev_priv,
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+ u64 start, int num_entries, enum i915_cache_level level)
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+{
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+ struct gvt_shared_page *shared_page = dev_priv->shared_page;
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+
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+ writeq(start, &shared_page->pv_ggtt.start);
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+ writeq(num_entries, &shared_page->pv_ggtt.length);
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+ writel(level, &shared_page->pv_ggtt.cache_level);
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+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_GGTT_INSERT);
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+}
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+
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static void gen8_ggtt_insert_page(struct i915_address_space *vm,
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dma_addr_t addr,
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u64 offset,
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@@ -2525,6 +2536,11 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
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gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
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+ if (PVMMIO_LEVEL(vm->i915, PVMMIO_GGTT_UPDATE)) {
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+ vgpu_ggtt_insert(vm->i915, offset, 1, level);
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+ return;
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+ }
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+
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ggtt->invalidate(vm->i915);
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}
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@@ -2549,6 +2565,20 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
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for_each_sgt_dma(addr, sgt_iter, vma->pages)
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gen8_set_pte(gtt_entries++, pte_encode | addr);
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+ if (PVMMIO_LEVEL(vm->i915, PVMMIO_GGTT_UPDATE)) {
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+ int num_entries = gtt_entries -
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+ ((gen8_pte_t __iomem *)ggtt->gsm +
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+ (vma->node.start >> PAGE_SHIFT));
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+ /*
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+ * Sometimes number of entries does not match vma node size.
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+ * Pass number of pte entries instead.
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+ */
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+ vgpu_ggtt_insert(vm->i915, vma->node.start,
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+ num_entries, level);
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+ return;
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+ }
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+
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+
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/*
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* We want to flush the TLBs only after we're certain all the PTE
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* updates have finished.
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@@ -2622,6 +2652,16 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm,
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for (i = 0; i < num_entries; i++)
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gen8_set_pte(>t_base[i], scratch_pte);
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+
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+ if (PVMMIO_LEVEL(vm->i915, PVMMIO_GGTT_UPDATE)) {
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+ struct drm_i915_private *dev_priv = vm->i915;
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+ struct gvt_shared_page *shared_page = dev_priv->shared_page;
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+
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+ writeq(start, &shared_page->pv_ggtt.start);
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+ writeq(length, &shared_page->pv_ggtt.length);
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+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_GGTT_CLEAR);
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+ }
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+
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}
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static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
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diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
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index 82ab32e87805..c15d4578bb5f 100644
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--- a/drivers/gpu/drm/i915/i915_pvinfo.h
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+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
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@@ -49,6 +49,8 @@ enum vgt_g2v_type {
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VGT_G2V_PPGTT_L4_ALLOC,
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VGT_G2V_PPGTT_L4_CLEAR,
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VGT_G2V_PPGTT_L4_INSERT,
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+ VGT_G2V_GGTT_INSERT,
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+ VGT_G2V_GGTT_CLEAR,
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VGT_G2V_MAX,
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};
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@@ -89,6 +91,12 @@ struct pv_ppgtt_update {
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u32 cache_level;
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};
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+struct pv_ggtt_update {
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+ u64 start;
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+ u64 length;
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+ u32 cache_level;
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+};
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+
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/* shared page(4KB) between gvt and VM, located at the first page next
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* to MMIO region(2MB size normally).
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*/
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@@ -98,7 +106,8 @@ struct gvt_shared_page {
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struct pv_plane_update pv_plane;
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struct pv_plane_wm_update pv_plane_wm;
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struct pv_ppgtt_update pv_ppgtt;
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- u32 rsvd2[0x400 - 40];
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+ struct pv_ggtt_update pv_ggtt;
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+ u32 rsvd2[0x400 - 46];
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};
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#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
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@@ -111,6 +120,7 @@ enum pvmmio_levels {
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PVMMIO_PLANE_UPDATE = 0x2,
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PVMMIO_PLANE_WM_UPDATE = 0x4,
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PVMMIO_PPGTT_UPDATE = 0x10,
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+ PVMMIO_GGTT_UPDATE = 0x20,
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};
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/*
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--
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https://clearlinux.org
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