161 lines
4.7 KiB
Diff
161 lines
4.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Zhipeng Gong <zhipeng.gong@intel.com>
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Date: Fri, 14 Sep 2018 16:10:20 +0800
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Subject: [PATCH] drm/i915/gvt: notify ppgtt update through g2v
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This patch extends g2v notification to notify host GVT-g of
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ppgtt update from guest, including alloc_4lvl, clear_4lv4 and
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insert_4lvl. It uses shared page to pass the additional params.
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This patch also add one new pvmmio level to control ppgtt update.
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This patch is needed for both uos and sos
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v2:
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- create a struct for ppggt update in shared page.
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- use multiple notifications in case insert size is too big.
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v3:
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- not pass pd pages, let GVT-g read from guest memory instead.
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v4:
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- not change rsvd2 type.
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v5:
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- pass cache_level to GVT-g
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Tracked-On: #874
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Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com>
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/i915_gem_gtt.c | 38 +++++++++++++++++++++++++++++
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drivers/gpu/drm/i915/i915_pvinfo.h | 14 ++++++++++-
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2 files changed, 51 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
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index b35af8c055e1..cb940a583c14 100644
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--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
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+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
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@@ -999,6 +999,8 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
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struct i915_pml4 *pml4 = &ppgtt->pml4;
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struct i915_page_directory_pointer *pdp;
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unsigned int pml4e;
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+ u64 orig_start = start;
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+ u64 orig_length = length;
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GEM_BUG_ON(!use_4lvl(vm));
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@@ -1012,6 +1014,17 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
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free_pdp(vm, pdp);
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}
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+
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+ if (PVMMIO_LEVEL(vm->i915, PVMMIO_PPGTT_UPDATE)) {
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+ struct drm_i915_private *dev_priv = vm->i915;
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+ struct pv_ppgtt_update *pv_ppgtt =
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+ &dev_priv->shared_page->pv_ppgtt;
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+
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+ writeq(px_dma(pml4), &pv_ppgtt->pdp);
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+ writeq(orig_start, &pv_ppgtt->start);
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+ writeq(orig_length, &pv_ppgtt->length);
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+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
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+ }
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}
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static inline struct sgt_dma {
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@@ -1251,6 +1264,18 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
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flags))
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GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
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+ if (PVMMIO_LEVEL(vm->i915, PVMMIO_PPGTT_UPDATE)) {
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+ struct drm_i915_private *dev_priv = vm->i915;
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+ struct pv_ppgtt_update *pv_ppgtt =
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+ &dev_priv->shared_page->pv_ppgtt;
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+
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+ writeq(px_dma(&ppgtt->pml4), &pv_ppgtt->pdp);
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+ writeq(vma->node.start, &pv_ppgtt->start);
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+ writeq(vma->node.size, &pv_ppgtt->length);
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+ writel(cache_level, &pv_ppgtt->cache_level);
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+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
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+ }
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+
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vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
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}
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}
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@@ -1499,6 +1524,8 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
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u64 from = start;
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u32 pml4e;
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int ret;
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+ u64 orig_start = start;
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+ u64 orig_length = length;
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gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
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if (pml4->pdps[pml4e] == vm->scratch_pdp) {
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@@ -1515,6 +1542,17 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
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goto unwind_pdp;
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}
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+ if (PVMMIO_LEVEL(vm->i915, PVMMIO_PPGTT_UPDATE)) {
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+ struct drm_i915_private *dev_priv = vm->i915;
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+ struct pv_ppgtt_update *pv_ppgtt =
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+ &dev_priv->shared_page->pv_ppgtt;
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+
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+ writeq(px_dma(pml4), &pv_ppgtt->pdp);
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+ writeq(orig_start, &pv_ppgtt->start);
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+ writeq(orig_length, &pv_ppgtt->length);
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+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
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+ }
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+
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return 0;
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unwind_pdp:
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diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
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index 740b2da14186..9c76cab07010 100644
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--- a/drivers/gpu/drm/i915/i915_pvinfo.h
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+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
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@@ -46,6 +46,9 @@ enum vgt_g2v_type {
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VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
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VGT_G2V_EXECLIST_CONTEXT_CREATE,
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VGT_G2V_EXECLIST_CONTEXT_DESTROY,
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+ VGT_G2V_PPGTT_L4_ALLOC,
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+ VGT_G2V_PPGTT_L4_CLEAR,
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+ VGT_G2V_PPGTT_L4_INSERT,
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VGT_G2V_MAX,
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};
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@@ -72,6 +75,13 @@ struct pv_plane_update {
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u32 plane_ctl;
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};
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+struct pv_ppgtt_update {
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+ u64 pdp;
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+ u64 start;
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+ u64 length;
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+ u32 cache_level;
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+};
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+
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/* shared page(4KB) between gvt and VM, located at the first page next
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* to MMIO region(2MB size normally).
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*/
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@@ -79,7 +89,8 @@ struct gvt_shared_page {
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u32 elsp_data[4];
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u32 reg_addr;
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struct pv_plane_update pv_plane;
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- u32 rsvd2[0x400 - 21];
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+ struct pv_ppgtt_update pv_ppgtt;
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+ u32 rsvd2[0x400 - 30];
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};
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#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
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@@ -90,6 +101,7 @@ struct gvt_shared_page {
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enum pvmmio_levels {
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PVMMIO_ELSP_SUBMIT = 0x1,
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PVMMIO_PLANE_UPDATE = 0x2,
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+ PVMMIO_PPGTT_UPDATE = 0x10,
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};
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/*
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--
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https://clearlinux.org
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