163 lines
5.2 KiB
Diff
163 lines
5.2 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Fei Jiang <fei.jiang@intel.com>
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Date: Fri, 14 Sep 2018 16:10:20 +0800
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Subject: [PATCH] drm/i915/gvt: pvmmio optimization for plane update
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It is performance optimization to reduce plane related register trap
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counter. When update plane, multiple plane related registers are updated
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together, optimize it to firstly cache all register values in share page,
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then only PLANE_SURF register writing is trapped. Plane pvmmio level is
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PVMMIO_PLANE_UPDATE.
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Patch for both SOS and UOS.
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V2: add memset tmp_plane to be more safer and add more commit description
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Signed-off-by: Fei Jiang <fei.jiang@intel.com>
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Reviewed-by: Min He <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/i915_pvinfo.h | 27 +++++++++++-
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drivers/gpu/drm/i915/intel_sprite.c | 68 +++++++++++++++++++++++++++++
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2 files changed, 94 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
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index c1089bdedd2e..740b2da14186 100644
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--- a/drivers/gpu/drm/i915/i915_pvinfo.h
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+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
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@@ -49,13 +49,37 @@ enum vgt_g2v_type {
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VGT_G2V_MAX,
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};
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+#define PLANE_COLOR_CTL_BIT (1 << 0)
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+#define PLANE_KEY_BIT (1 << 1)
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+#define PLANE_SCALER_BIT (1 << 2)
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+
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+struct pv_plane_update {
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+ u32 flags;
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+ u32 plane_color_ctl;
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+ u32 plane_key_val;
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+ u32 plane_key_max;
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+ u32 plane_key_msk;
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+ u32 plane_offset;
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+ u32 plane_stride;
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+ u32 plane_size;
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+ u32 plane_aux_dist;
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+ u32 plane_aux_offset;
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+ u32 ps_ctrl;
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+ u32 ps_pwr_gate;
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+ u32 ps_win_ps;
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+ u32 ps_win_sz;
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+ u32 plane_pos;
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+ u32 plane_ctl;
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+};
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+
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/* shared page(4KB) between gvt and VM, located at the first page next
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* to MMIO region(2MB size normally).
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*/
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struct gvt_shared_page {
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u32 elsp_data[4];
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u32 reg_addr;
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- u32 rsvd2[0x400 - 5];
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+ struct pv_plane_update pv_plane;
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+ u32 rsvd2[0x400 - 21];
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};
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#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
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@@ -65,6 +89,7 @@ struct gvt_shared_page {
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*/
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enum pvmmio_levels {
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PVMMIO_ELSP_SUBMIT = 0x1,
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+ PVMMIO_PLANE_UPDATE = 0x2,
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};
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/*
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diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
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index 11b7afc0a0d3..4b89ba3e021c 100644
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--- a/drivers/gpu/drm/i915/intel_sprite.c
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+++ b/drivers/gpu/drm/i915/intel_sprite.c
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@@ -232,6 +232,68 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
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#endif
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}
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+static void pv_update_plane_reg(struct intel_plane *plane,
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+ u32 stride, uint32_t src_w, uint32_t src_h,
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+ uint32_t crtc_w, uint32_t crtc_h, u32 aux_stride,
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+ const struct intel_crtc_state *crtc_state,
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+ const struct intel_plane_state *plane_state)
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+{
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+ int i;
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+ struct pv_plane_update tmp_plane;
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+ uint32_t x = plane_state->main.x;
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+ uint32_t y = plane_state->main.y;
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+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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+ u32 __iomem *pv_plane = (u32 *)&(dev_priv->shared_page->pv_plane);
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+
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+ memset(&tmp_plane, 0, sizeof(struct pv_plane_update));
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+ if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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+ tmp_plane.flags |= PLANE_COLOR_CTL_BIT;
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+ tmp_plane.plane_color_ctl = PLANE_COLOR_PIPE_GAMMA_ENABLE |
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+ PLANE_COLOR_PIPE_CSC_ENABLE |
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+ PLANE_COLOR_PLANE_GAMMA_DISABLE;
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+ }
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+
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+ if (plane_state->ckey.flags) {
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+ tmp_plane.flags |= PLANE_KEY_BIT;
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+ tmp_plane.plane_key_val = plane_state->ckey.min_value;
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+ tmp_plane.plane_key_max = plane_state->ckey.max_value;
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+ tmp_plane.plane_key_msk = plane_state->ckey.channel_mask;
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+ }
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+
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+ tmp_plane.plane_offset = (y << 16) | x;
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+ tmp_plane.plane_stride = stride;
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+ tmp_plane.plane_size = (src_h << 16) | src_w;
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+ tmp_plane.plane_aux_dist =
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+ (plane_state->aux.offset - plane_state->main.offset) |
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+ aux_stride;
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+ tmp_plane.plane_aux_offset =
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+ (plane_state->aux.y << 16) | plane_state->aux.x;
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+
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+ /* program plane scaler */
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+ if (plane_state->scaler_id >= 0) {
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+ tmp_plane.flags |= PLANE_SCALER_BIT;
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+ tmp_plane.ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane->id) |
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+ crtc_state->scaler_state.scalers[plane_state->scaler_id].mode;
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+ tmp_plane.ps_pwr_gate = 0;
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+ tmp_plane.ps_win_ps =
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+ (plane_state->base.dst.x1 << 16) | plane_state->base.dst.y1;
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+ tmp_plane.ps_win_sz = ((crtc_w + 1) << 16) | (crtc_h + 1);
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+ tmp_plane.plane_pos = 0;
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+ } else {
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+ tmp_plane.plane_pos =
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+ (plane_state->base.dst.y1 << 16) | plane_state->base.dst.x1;
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+ }
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+
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+ tmp_plane.plane_ctl = plane_state->ctl;
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+
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+ spin_lock(&dev_priv->shared_page_lock);
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+ for (i = 0; i < sizeof(struct pv_plane_update) / 4; i++)
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+ writel(*((u32 *)(&tmp_plane) + i), pv_plane + i);
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+ I915_WRITE_FW(PLANE_SURF(plane->pipe, plane->id),
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+ intel_plane_ggtt_offset(plane_state) + plane_state->main.offset);
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+ spin_unlock(&dev_priv->shared_page_lock);
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+}
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+
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void
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skl_update_plane(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state,
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@@ -268,6 +330,12 @@ skl_update_plane(struct intel_plane *plane,
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crtc_w--;
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crtc_h--;
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+ if (PVMMIO_LEVEL(dev_priv, PVMMIO_PLANE_UPDATE)) {
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+ pv_update_plane_reg(plane, stride, src_w, src_h,
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+ crtc_w, crtc_h, aux_stride, crtc_state, plane_state);
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+ return;
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+ }
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+
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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--
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https://clearlinux.org
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