147 lines
5.3 KiB
Diff
147 lines
5.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Min He <min.he@intel.com>
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Date: Fri, 14 Sep 2018 16:10:18 +0800
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Subject: [PATCH] drm/i915/gvt: Added error interrupt handler for GVT-g guest
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An draft version of adding error interrupt handler in GVT-g guest, to
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trigger a GPU reset when receiving the CS error interrupt.
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v2: Updated by JH - made the worker object local to the engine rather
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than a global. Also, don't re-initialise it in the interrupt handler
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otherwise null pointer dereferences ensue when the interrupts occur
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too quickly.
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In the Xen virtualised environment, the TDR is a co-operative effort
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between the host and guest domains. The actual detection is done
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entirely by the host as only it really knows what the hardware is
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doing. The guest still needs to do all the recovery processing when
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informed about a TDR event occuring by the host. However, the guest
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should not attempt to do the detection itself.
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Change-Id: I3edac5211f9878725b14abaab7cacf9048ccd620
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Signed-off-by: Min He <min.he@intel.com>
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Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
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Signed-off-by: Satyeshwar Singh <satyeshwar.singh@intel.com>
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Reviewed-on:
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
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drivers/gpu/drm/i915/i915_irq.c | 19 +++++++++++++++++++
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drivers/gpu/drm/i915/intel_hangcheck.c | 3 +++
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drivers/gpu/drm/i915/intel_lrc.c | 12 ++++++++++++
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drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
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5 files changed, 38 insertions(+)
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diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
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index e063e98d1e82..b2e0c2348882 100644
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--- a/drivers/gpu/drm/i915/i915_debugfs.c
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+++ b/drivers/gpu/drm/i915/i915_debugfs.c
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@@ -4004,6 +4004,9 @@ i915_wedged_set(void *data, u64 val)
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struct intel_engine_cs *engine;
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unsigned int tmp;
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+ if (intel_vgpu_active(i915))
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+ return -EINVAL;
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+
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/*
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* There is no safeguard against this debugfs entry colliding
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* with the hangcheck calling same i915_handle_error() in
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diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
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index 42bf8131c124..5428de8e8c59 100644
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--- a/drivers/gpu/drm/i915/i915_irq.c
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+++ b/drivers/gpu/drm/i915/i915_irq.c
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@@ -1518,6 +1518,12 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
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tasklet |= USES_GUC_SUBMISSION(engine->i915);
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}
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+ if ((iir & (GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) &&
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+ intel_vgpu_active(engine->i915)) {
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+ queue_work(system_highpri_wq, &engine->reset_work);
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+ return;
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+ }
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+
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if (tasklet)
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tasklet_hi_schedule(&engine->execlists.tasklet);
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}
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@@ -4160,6 +4166,19 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
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if (HAS_L3_DPF(dev_priv))
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gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
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+ if (intel_vgpu_active(dev_priv)) {
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+ gt_interrupts[0] |= GT_RENDER_CS_MASTER_ERROR_INTERRUPT <<
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+ GEN8_RCS_IRQ_SHIFT |
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+ GT_RENDER_CS_MASTER_ERROR_INTERRUPT <<
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+ GEN8_BCS_IRQ_SHIFT;
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+ gt_interrupts[1] |= GT_RENDER_CS_MASTER_ERROR_INTERRUPT <<
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+ GEN8_VCS1_IRQ_SHIFT |
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+ GT_RENDER_CS_MASTER_ERROR_INTERRUPT <<
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+ GEN8_VCS2_IRQ_SHIFT;
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+ gt_interrupts[3] |= GT_RENDER_CS_MASTER_ERROR_INTERRUPT <<
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+ GEN8_VECS_IRQ_SHIFT;
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+ }
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+
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dev_priv->pm_ier = 0x0;
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dev_priv->pm_imr = ~dev_priv->pm_ier;
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GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
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diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
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index 2fc7a0dd0df9..1f7da1cfd4b2 100644
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--- a/drivers/gpu/drm/i915/intel_hangcheck.c
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+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
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@@ -418,6 +418,9 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
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if (!i915_modparams.enable_hangcheck)
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return;
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+ if (intel_vgpu_active(dev_priv))
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+ return;
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+
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if (!READ_ONCE(dev_priv->gt.awake))
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return;
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diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
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index 13e97faabaa7..c8d5324f2d38 100644
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--- a/drivers/gpu/drm/i915/intel_lrc.c
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+++ b/drivers/gpu/drm/i915/intel_lrc.c
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@@ -2395,6 +2395,16 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
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engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
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}
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+static void i915_error_reset(struct work_struct *work) {
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+ struct intel_engine_cs *engine =
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+ container_of(work, struct intel_engine_cs,
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+ reset_work);
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+ i915_handle_error(engine->i915, 1 << engine->id,
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+ I915_ERROR_CAPTURE,
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+ "Received error interrupt from engine %d",
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+ engine->id);
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+}
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+
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static void
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logical_ring_setup(struct intel_engine_cs *engine)
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{
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@@ -2408,6 +2418,8 @@ logical_ring_setup(struct intel_engine_cs *engine)
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logical_ring_default_vfuncs(engine);
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logical_ring_default_irqs(engine);
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+
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+ INIT_WORK(&engine->reset_work, i915_error_reset);
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}
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static bool csb_force_mmio(struct drm_i915_private *i915)
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diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
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index eaf1a161bc96..4f39f6b5d1e0 100644
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--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
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+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
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@@ -567,6 +567,7 @@ struct intel_engine_cs {
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} semaphore;
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struct intel_engine_execlists execlists;
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+ struct work_struct reset_work;
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/* Contexts are pinned whilst they are active on the GPU. The last
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* context executed remains active whilst the GPU is idle - the
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--
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https://clearlinux.org
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