38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Fei Jiang <fei.jiang@intel.com>
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Date: Fri, 29 Dec 2017 19:14:16 +0800
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Subject: [PATCH] drm/i915/gvt: hard code Pipe B plane owner to UOS
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It is a work around patch due to plane restriction patches are not porting
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Change-Id: If09ff8c40254ec275dc2d9b9674d7267d306a7e7
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Signed-off-by: Fei Jiang <fei.jiang@intel.com>
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Reviewed-on:
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/gvt/acrngt.c | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/acrngt.c b/drivers/gpu/drm/i915/gvt/acrngt.c
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index fec5751a4bed..346a676d77bc 100644
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--- a/drivers/gpu/drm/i915/gvt/acrngt.c
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+++ b/drivers/gpu/drm/i915/gvt/acrngt.c
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@@ -431,6 +431,13 @@ static int acrngt_sysfs_add_instance(struct acrngt_hvm_params *vp)
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struct acrngt_hvm_dev *info;
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struct intel_vgpu_type type = acrngt_priv.gvt->types[0];
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+
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+ /* todo: wa patch due to plane restriction patches are not porting */
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+ acrngt_priv.gvt->pipe_info[1].plane_owner[0] = 1;
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+ acrngt_priv.gvt->pipe_info[1].plane_owner[1] = 1;
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+ acrngt_priv.gvt->pipe_info[1].plane_owner[2] = 1;
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+ acrngt_priv.gvt->pipe_info[1].plane_owner[3] = 1;
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+
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type.low_gm_size = vp->aperture_sz * VMEM_1MB;
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type.high_gm_size = (vp->gm_sz - vp->aperture_sz) * VMEM_1MB;
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type.fence = vp->fence_sz;
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--
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https://clearlinux.org
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