98 lines
3.4 KiB
Diff
98 lines
3.4 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Pei Zhang <pei.zhang@intel.com>
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Date: Fri, 14 Sep 2018 16:10:17 +0800
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Subject: [PATCH] drm/i915/gvt: add some MMIO value initialization
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There are some virtual MMIO registers contains static value which won't
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be changed by guest writing. Those registers could be optimized with a
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static value initialization, and do nothing in write handler.
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Change-Id: I1a85f717ef23c171651f1a1cad5c73880d538e3d
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Signed-off-by: Pei Zhang <pei.zhang@intel.com>
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Acknowledged-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
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Reviewed-on:
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Reviewed-by: He, Min <min.he@intel.com>
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/gvt/handlers.c | 32 +++++++----------------------
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drivers/gpu/drm/i915/gvt/mmio.c | 9 ++++++++
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2 files changed, 16 insertions(+), 25 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
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index e1855328eba6..495d6a298924 100644
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--- a/drivers/gpu/drm/i915/gvt/handlers.c
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+++ b/drivers/gpu/drm/i915/gvt/handlers.c
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@@ -413,27 +413,9 @@ static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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return 0;
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}
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-static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
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+static int mmio_write_empty(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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- switch (offset) {
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- case 0xe651c:
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- case 0xe661c:
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- case 0xe671c:
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- case 0xe681c:
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- vgpu_vreg(vgpu, offset) = 1 << 17;
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- break;
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- case 0xe6c04:
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- vgpu_vreg(vgpu, offset) = 0x3;
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- break;
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- case 0xe6e1c:
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- vgpu_vreg(vgpu, offset) = 0x2f << 16;
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- break;
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- default:
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- return -EINVAL;
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- }
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-
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- read_vreg(vgpu, offset, p_data, bytes);
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return 0;
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}
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@@ -2240,12 +2222,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
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MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
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- MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
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- MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
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- MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
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- MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
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- MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
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- MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
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+ MMIO_DH(_MMIO(0xe651c), D_ALL, NULL, mmio_write_empty);
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+ MMIO_DH(_MMIO(0xe661c), D_ALL, NULL, mmio_write_empty);
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+ MMIO_DH(_MMIO(0xe671c), D_ALL, NULL, mmio_write_empty);
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+ MMIO_DH(_MMIO(0xe681c), D_ALL, NULL, mmio_write_empty);
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+ MMIO_DH(_MMIO(0xe6c04), D_ALL, NULL, mmio_write_empty);
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+ MMIO_DH(_MMIO(0xe6e1c), D_ALL, NULL, mmio_write_empty);
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MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
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PORTA_HOTPLUG_STATUS_MASK
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diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
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index 9bb9a85c992c..4149eae235b5 100644
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--- a/drivers/gpu/drm/i915/gvt/mmio.c
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+++ b/drivers/gpu/drm/i915/gvt/mmio.c
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@@ -282,6 +282,15 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
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memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
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}
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+ /* below vreg init value are got from handler.c,
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+ * which won't change during vgpu life cycle
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+ */
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+ vgpu_vreg(vgpu, 0xe651c) = 1 << 17;
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+ vgpu_vreg(vgpu, 0xe661c) = 1 << 17;
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+ vgpu_vreg(vgpu, 0xe671c) = 1 << 17;
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+ vgpu_vreg(vgpu, 0xe681c) = 1 << 17;
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+ vgpu_vreg(vgpu, 0xe6c04) = 3;
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+ vgpu_vreg(vgpu, 0xe6e1c) = 0x2f << 16;
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}
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/**
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--
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https://clearlinux.org
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