108 lines
3.3 KiB
Diff
108 lines
3.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Mousumi Jana <mousumix.jana@intel.com>
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Date: Tue, 12 Sep 2017 17:18:44 +0530
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Subject: [PATCH] ASoC: Intel: Set all I2S ports to slave mode after DSP power
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up in BXTP
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During DSP power up sequences, the I2S ports default to Master mode.
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This drives frame sync and bit clock high and may cause distortion
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issues on peripherals in some boards.
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To prevent this, the ports should be set slave mode before the DSP boot.
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Change-Id: Id8f96989d35674acad89f7080f58e7682bcd81dc
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Signed-off-by: Sameer Sharma <sameerx.sharma@intel.com>
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Signed-off-by: Mousumi Jana <mousumix.jana@intel.com>
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Signed-off-by: Mohit Sinha <mohit.sinha@intel.com>
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Reviewed-on:
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Reviewed-by: Singh, Guneshwor O <guneshwor.o.singh@intel.com>
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Reviewed-by: Shaik, Kareem M <kareem.m.shaik@intel.com>
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Reviewed-by: Gogineni, GiribabuX <giribabux.gogineni@intel.com>
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Reviewed-by: Koul, Vinod <vinod.koul@intel.com>
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Reviewed-by: audio_build
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Tested-by: Sm, Bhadur A <bhadur.a.sm@intel.com>
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---
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sound/soc/intel/skylake/bxt-sst.c | 45 +++++++++++++++++++++++++++++++
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1 file changed, 45 insertions(+)
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diff --git a/sound/soc/intel/skylake/bxt-sst.c b/sound/soc/intel/skylake/bxt-sst.c
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index 406d278555f0..dd5453daa562 100644
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--- a/sound/soc/intel/skylake/bxt-sst.c
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+++ b/sound/soc/intel/skylake/bxt-sst.c
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@@ -32,6 +32,15 @@
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#define BXT_ROM_INIT 0x5
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#define BXT_ADSP_SRAM0_BASE 0x80000
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+/* BXT SSP/I2S Registers */
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+#define I2S_SSC1_REG_OFF BIT(2)
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+#define SET_SLAVE_MASK GENMASK(25, 24)
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+
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+/*BXT I2S Clock Gating*/
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+#define BXT_DSP_CLK_CTL 0x378
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+#define BXT_DISABLE_4_SSP_CLK_GT GENMASK(21, 18)
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+#define BXT_DISABLE_ALL_SSP_CLK_GT GENMASK(23, 18)
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+
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/* Trace Buffer Window */
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#define BXT_ADSP_SRAM2_BASE 0x0C0000
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#define BXT_ADSP_W2_SIZE 0x2000
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@@ -52,6 +61,36 @@
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#define BXT_FW_ROM_INIT_RETRY 3
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+#define GET_SSP_BASE(N) (N > 4 ? 0x2000 : 0x4000)
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+
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+#define BXTP_NUM_I2S_PORTS 6
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+
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+static void bxt_set_ssp_slave(struct sst_dsp *ctx)
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+{
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+ u32 mask, i2s_base_addr;
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+ int i;
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+
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+ if (BXTP_NUM_I2S_PORTS == 4)
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+ mask = BXT_DISABLE_4_SSP_CLK_GT;
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+ else
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+ mask = BXT_DISABLE_ALL_SSP_CLK_GT;
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+
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+ /* disable clock gating on all SSPs */
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+ sst_dsp_shim_update_bits_unlocked(ctx,
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+ BXT_DSP_CLK_CTL, mask, mask);
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+
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+ /* set all SSPs to slave */
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+ i2s_base_addr = GET_SSP_BASE(BXTP_NUM_I2S_PORTS);
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+ for (i = 0; i < BXTP_NUM_I2S_PORTS; i++) {
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+ sst_dsp_shim_update_bits_unlocked(ctx,
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+ (i2s_base_addr + (i * 0x1000) + I2S_SSC1_REG_OFF),
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+ SET_SLAVE_MASK, SET_SLAVE_MASK);
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+ }
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+
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+ /* re-enable clock gating */
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+ sst_dsp_shim_update_bits_unlocked(ctx, BXT_DSP_CLK_CTL, mask, 0);
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+}
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+
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static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
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{
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return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
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@@ -134,6 +173,9 @@ static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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goto base_fw_load_failed;
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}
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+ /* DSP is powered up, set all SSPs to slave mode */
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+ bxt_set_ssp_slave(ctx);
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+
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/* Step 2: Purge FW request */
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
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(BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
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@@ -448,6 +490,9 @@ static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
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if (core_id == SKL_DSP_CORE0_ID) {
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+ /* set all SSPs to slave mode */
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+ bxt_set_ssp_slave(ctx);
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+
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/*
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* Enable interrupt after SPA is set and before
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* DSP is unstalled
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--
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https://clearlinux.org
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