From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: qianmenx Date: Tue, 21 May 2019 11:37:37 +0800 Subject: [PATCH] media: intel-ipu4: ox03a10: change metadata set change digital gain reg number to 3 of metadata Change-Id: Ifdd173db9a7f40088436a8a5acb2431363a2a508 Tracked-On: PKT-2588 Tracked-On: #JIIAP-801 Signed-off-by: qianmenx Signed-off-by: Meng Wei --- drivers/media/i2c/crlmodule/crl_ox03a10_common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h index 636ac23da3a3..484e89526226 100644 --- a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h +++ b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h @@ -532,9 +532,9 @@ static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = { { 0x483e, CRL_REG_LEN_08BIT, 0x02 },/* frame counter */ { 0x3501, CRL_REG_LEN_08BIT, 0x02 },/* DCG exp */ { 0x3581, CRL_REG_LEN_08BIT, 0x02 },/* VS exp */ - { 0x350a, CRL_REG_LEN_08BIT, 0x02 },/* HCG Dgain */ - { 0x354a, CRL_REG_LEN_08BIT, 0x02 },/* LCG Dgain */ - { 0x358a, CRL_REG_LEN_08BIT, 0x02 },/* VS Dgain */ + { 0x350a, CRL_REG_LEN_08BIT, 0x03 },/* HCG Dgain */ + { 0x354a, CRL_REG_LEN_08BIT, 0x03 },/* LCG Dgain */ + { 0x358a, CRL_REG_LEN_08BIT, 0x03 },/* VS Dgain */ { 0x3508, CRL_REG_LEN_08BIT, 0x02 },/* HCG Again */ { 0x3548, CRL_REG_LEN_08BIT, 0x02 },/* LCG Again */ { 0x3588, CRL_REG_LEN_08BIT, 0x02 },/* VS Again */ -- https://clearlinux.org