From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Meng Wei Date: Mon, 24 Dec 2018 11:56:05 +0800 Subject: [PATCH] media: intel-ipu4: ov495: OV2775+OV495 enablement single sensor OV2775 enable. Change-Id: I77b2117acf81a5dad8d9986d2ba8a8624797f85c Tracked-On: PKT-1691 Signed-off-by: lizhao7x Signed-off-by: Meng Wei --- .../i2c/crlmodule/crl_ov495_configuration.h | 284 ++++++++++++++++++ drivers/media/i2c/crlmodule/crlmodule-data.c | 2 + drivers/media/i2c/ti960.c | 12 +- drivers/media/platform/intel/Kconfig | 6 + .../media/platform/intel/ipu4-bxt-p-pdata.c | 123 ++++++++ 5 files changed, 423 insertions(+), 4 deletions(-) create mode 100644 drivers/media/i2c/crlmodule/crl_ov495_configuration.h diff --git a/drivers/media/i2c/crlmodule/crl_ov495_configuration.h b/drivers/media/i2c/crlmodule/crl_ov495_configuration.h new file mode 100644 index 000000000000..6884cf503bb4 --- /dev/null +++ b/drivers/media/i2c/crlmodule/crl_ov495_configuration.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2017 - 2018 Intel Corporation + * + * Author: Ying Chang + * Meng J Chen + * Zhaox Li + * + */ + +#ifndef __CRLMODULE_OV495_CONFIGURATION_H_ +#define __CRLMODULE_OV495_CONFIGURATION_H_ + +#include "crlmodule-sensor-ds.h" + +struct crl_sensor_detect_config ov495_sensor_detect_regset[] = { + { + .reg = {0x3000, CRL_REG_LEN_08BIT, 0xFF}, + .width = 8, + }, + { + .reg = {0x3001, CRL_REG_LEN_08BIT, 0xFF}, + .width = 8, + }, + { + .reg = {0x3002, CRL_REG_LEN_08BIT, 0xFF}, + .width = 8, + }, + { + .reg = {0x3003, CRL_REG_LEN_08BIT, 0xFF}, + .width = 8, + }, +}; + +static struct crl_pll_configuration ov495_pll_configurations[] = { + { + .input_clk = 27000000, + .op_sys_clk = 400000000, + .bitsperpixel = 16, + .pixel_rate_csi = 108000000, + .pixel_rate_pa = 108000000, /* pixel_rate = op_sys_clk*2 *csi_lanes/bitsperpixel */ + .csi_lanes = 4, + .comp_items = 0, + .ctrl_data = 0, + .pll_regs_items = 0, + .pll_regs = 0, + }, +}; + +static struct crl_subdev_rect_rep ov495_1280_1080_rects[] = { + { + .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY, + .in_rect.left = 0, + .in_rect.top = 0, + .in_rect.width = 1280, + .in_rect.height = 1080, + .out_rect.left = 0, + .out_rect.top = 0, + .out_rect.width = 1280, + .out_rect.height = 1080, + }, + { + .subdev_type = CRL_SUBDEV_TYPE_BINNER, + .in_rect.left = 0, + .in_rect.top = 0, + .in_rect.width = 1280, + .in_rect.height = 1080, + .out_rect.left = 0, + .out_rect.top = 0, + .out_rect.width = 1280, + .out_rect.height = 1080, + }, +}; + +static struct crl_subdev_rect_rep ov495_1920_1080_rects[] = { + { + .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY, + .in_rect.left = 0, + .in_rect.top = 0, + .in_rect.width = 1920, + .in_rect.height = 1080, + .out_rect.left = 0, + .out_rect.top = 0, + .out_rect.width = 1920, + .out_rect.height = 1080, + }, + { + .subdev_type = CRL_SUBDEV_TYPE_BINNER, + .in_rect.left = 0, + .in_rect.top = 0, + .in_rect.width = 1920, + .in_rect.height = 1080, + .out_rect.left = 0, + .out_rect.top = 0, + .out_rect.width = 1920, + .out_rect.height = 1080, + }, +}; + +static struct crl_register_write_rep ov495_1920x1080_regs[] = { + {0x3516, CRL_REG_LEN_08BIT, 0x00}, + {0x354d, CRL_REG_LEN_08BIT, 0x10}, + {0x354a, CRL_REG_LEN_08BIT, 0x1d}, + {0x0500, CRL_REG_LEN_08BIT, 0x00}, + {0x30c0, CRL_REG_LEN_08BIT, 0xe2}, + {0x0000, CRL_REG_LEN_DELAY, 0x0a}, + + {0x3516, CRL_REG_LEN_08BIT, 0x00}, + {0x354d, CRL_REG_LEN_08BIT, 0x10}, + {0x354a, CRL_REG_LEN_08BIT, 0x1d}, + {0x0500, CRL_REG_LEN_08BIT, 0x01}, + {0x30c0, CRL_REG_LEN_08BIT, 0xe2}, + {0x0000, CRL_REG_LEN_DELAY, 0x0a}, +}; + +static struct crl_register_write_rep ov495_1280x1080_regs[] = { + {0x3516, CRL_REG_LEN_08BIT, 0x00}, + {0x354d, CRL_REG_LEN_08BIT, 0x10}, + {0x354a, CRL_REG_LEN_08BIT, 0x1d}, + {0x7800, CRL_REG_LEN_08BIT, 0x00}, + {0x0500, CRL_REG_LEN_08BIT, 0x00}, + {0x0501, CRL_REG_LEN_08BIT, 0x01}, + {0x0502, CRL_REG_LEN_08BIT, 0x01}, + {0x0503, CRL_REG_LEN_08BIT, 0x40}, + {0x0504, CRL_REG_LEN_08BIT, 0x00}, + {0x0505, CRL_REG_LEN_08BIT, 0x00}, + {0x0506, CRL_REG_LEN_08BIT, 0x05}, + {0x0507, CRL_REG_LEN_08BIT, 0x00}, + {0x0508, CRL_REG_LEN_08BIT, 0x04}, + {0x0509, CRL_REG_LEN_08BIT, 0x38}, + {0x30c0, CRL_REG_LEN_08BIT, 0xc3}, + {0x0000, CRL_REG_LEN_DELAY, 0x0a}, +}; + +static struct crl_mode_rep ov495_modes[] = { + { + .sd_rects_items = ARRAY_SIZE(ov495_1280_1080_rects), + .sd_rects = ov495_1280_1080_rects, + .binn_hor = 1, + .binn_vert = 1, + .scale_m = 1, + .width = 1280, + .height = 1080, + .min_llp = 2250, + .min_fll = 1320, + .mode_regs_items = ARRAY_SIZE(ov495_1280x1080_regs), + .mode_regs = ov495_1280x1080_regs, + }, + { + .sd_rects_items = ARRAY_SIZE(ov495_1920_1080_rects), + .sd_rects = ov495_1920_1080_rects, + .binn_hor = 1, + .binn_vert = 1, + .scale_m = 1, + .width = 1920, + .height = 1080, + .min_llp = 2250, + .min_fll = 1320, + .mode_regs_items = ARRAY_SIZE(ov495_1920x1080_regs), + .mode_regs = ov495_1920x1080_regs, + }, +}; + +static struct crl_sensor_subdev_config ov495_sensor_subdevs[] = { + { + .subdev_type = CRL_SUBDEV_TYPE_BINNER, + .name = "ov495 binner", + }, + { + .subdev_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY, + .name = "ov495 pixel array", + } +}; + +static struct crl_sensor_limits ov495_sensor_limits = { + .x_addr_min = 0, + .y_addr_min = 0, + .x_addr_max = 1920, + .y_addr_max = 1080, + .min_frame_length_lines = 240, + .max_frame_length_lines = 65535, + .min_line_length_pixels = 320, + .max_line_length_pixels = 32752, +}; + +static struct crl_csi_data_fmt ov495_crl_csi_data_fmt[] = { + { + .code = MEDIA_BUS_FMT_YUYV8_1X16, + .pixel_order = CRL_PIXEL_ORDER_IGNORE, + .bits_per_pixel = 16, + }, + { + .code = MEDIA_BUS_FMT_UYVY8_1X16, + .pixel_order = CRL_PIXEL_ORDER_IGNORE, + .bits_per_pixel = 16, + }, +}; + +static struct crl_v4l2_ctrl ov495_v4l2_ctrls[] = { + { + .sd_type = CRL_SUBDEV_TYPE_BINNER, + .op_type = CRL_V4L2_CTRL_SET_OP, + .context = SENSOR_IDLE, + .ctrl_id = V4L2_CID_LINK_FREQ, + .name = "V4L2_CID_LINK_FREQ", + .type = CRL_V4L2_CTRL_TYPE_MENU_INT, + .data.v4l2_int_menu.def = 0, + .data.v4l2_int_menu.max = 0, + .data.v4l2_int_menu.menu = 0, + .flags = 0, + .impact = CRL_IMPACTS_NO_IMPACT, + .regs_items = 0, + .regs = 0, + .dep_items = 0, + .dep_ctrls = 0, + }, + { + .sd_type = CRL_SUBDEV_TYPE_PIXEL_ARRAY, + .op_type = CRL_V4L2_CTRL_GET_OP, + .context = SENSOR_POWERED_ON, + .ctrl_id = V4L2_CID_PIXEL_RATE, + .name = "V4L2_CID_PIXEL_RATE_PA", + .type = CRL_V4L2_CTRL_TYPE_INTEGER, + .data.std_data.min = 0, + .data.std_data.max = INT_MAX, + .data.std_data.step = 1, + .data.std_data.def = 0, + .flags = 0, + .impact = CRL_IMPACTS_NO_IMPACT, + .regs_items = 0, + .regs = 0, + .dep_items = 0, + .dep_ctrls = 0, + }, + { + .sd_type = CRL_SUBDEV_TYPE_BINNER, + .op_type = CRL_V4L2_CTRL_GET_OP, + .context = SENSOR_POWERED_ON, + .ctrl_id = V4L2_CID_PIXEL_RATE, + .name = "V4L2_CID_PIXEL_RATE_CSI", + .type = CRL_V4L2_CTRL_TYPE_INTEGER, + .data.std_data.min = 0, + .data.std_data.max = INT_MAX, + .data.std_data.step = 1, + .data.std_data.def = 0, + .flags = 0, + .impact = CRL_IMPACTS_NO_IMPACT, + .regs_items = 0, + .regs = 0, + .dep_items = 0, + .dep_ctrls = 0, + }, +}; + +struct crl_sensor_configuration ov495_crl_configuration = { + + .subdev_items = ARRAY_SIZE(ov495_sensor_subdevs), + .subdevs = ov495_sensor_subdevs, + + .pll_config_items = ARRAY_SIZE(ov495_pll_configurations), + .pll_configs = ov495_pll_configurations, + + .id_reg_items = ARRAY_SIZE(ov495_sensor_detect_regset), + .id_regs = ov495_sensor_detect_regset, + + .sensor_limits = &ov495_sensor_limits, + + .modes_items = ARRAY_SIZE(ov495_modes), + .modes = ov495_modes, + + .streamon_regs_items = 0, + .streamon_regs = 0, + + .streamoff_regs_items = 0, + .streamoff_regs = 0, + + .v4l2_ctrls_items = ARRAY_SIZE(ov495_v4l2_ctrls), + .v4l2_ctrl_bank = ov495_v4l2_ctrls, + + .csi_fmts_items = ARRAY_SIZE(ov495_crl_csi_data_fmt), + .csi_fmts = ov495_crl_csi_data_fmt, + +}; + +#endif /* __CRLMODULE_OV495_CONFIGURATION_H_ */ diff --git a/drivers/media/i2c/crlmodule/crlmodule-data.c b/drivers/media/i2c/crlmodule/crlmodule-data.c index d4143a53a7fa..2c07ca06a83a 100644 --- a/drivers/media/i2c/crlmodule/crlmodule-data.c +++ b/drivers/media/i2c/crlmodule/crlmodule-data.c @@ -32,6 +32,7 @@ #include "crl_ar023z_configuration.h" #include "crl_ov2775_configuration.h" #include "crl_ox03a10_configuration.h" +#include "crl_ov495_configuration.h" static const struct crlmodule_sensors supported_sensors[] = { { "i2c-SONY214A:00", "imx214", &imx214_crl_configuration }, @@ -70,6 +71,7 @@ static const struct crlmodule_sensors supported_sensors[] = { { "AR023Z", "ar023z", &ar023z_crl_configuration }, { "OV2775", "ov2775", &ov2775_crl_configuration }, { "OX03A10", "ox03a10", &ox03a10_crl_configuration }, + { "OV495", "ov495", &ov495_crl_configuration}, }; /* diff --git a/drivers/media/i2c/ti960.c b/drivers/media/i2c/ti960.c index 2761dbe17bc8..12cacab51eef 100644 --- a/drivers/media/i2c/ti960.c +++ b/drivers/media/i2c/ti960.c @@ -76,6 +76,8 @@ static const u8 ti960_op_sys_clock_reg_val[] = { * orders must be defined. */ static const struct ti960_csi_data_format va_csi_data_formats[] = { + { MEDIA_BUS_FMT_YUYV8_1X16, 16, 16, PIXEL_ORDER_GBRG, 0x1e}, + { MEDIA_BUS_FMT_UYVY8_1X16, 16, 16, PIXEL_ORDER_GBRG, 0X1e}, { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, PIXEL_ORDER_GRBG, 0x2e }, { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, PIXEL_ORDER_RGGB, 0x2e }, { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, PIXEL_ORDER_BGGR, 0x2e }, @@ -91,6 +93,8 @@ static const struct ti960_csi_data_format va_csi_data_formats[] = { }; static const uint32_t ti960_supported_codes_pad[] = { + MEDIA_BUS_FMT_YUYV8_1X16, + MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_SBGGR16_1X16, MEDIA_BUS_FMT_SGBRG16_1X16, MEDIA_BUS_FMT_SGRBG16_1X16, @@ -1203,11 +1207,11 @@ static int ti960_probe(struct i2c_client *client, return -ENOMEM; for (i = 0; i < va->nstreams; i++) { - va->ti960_route[i].sink_pad = i / 2; - va->ti960_route[i].sink_stream = i % 2; + va->ti960_route[i].sink_pad = i; + va->ti960_route[i].sink_stream = i; va->ti960_route[i].source_pad = TI960_PAD_SOURCE; - va->ti960_route[i].source_stream = i % 2; - va->ti960_route[i].flags = MEDIA_PAD_FL_MULTIPLEX; + va->ti960_route[i].source_stream = i; +// va->ti960_route[i].flags = MEDIA_PAD_FL_MULTIPLEX; } va->regmap8 = devm_regmap_init_i2c(client, diff --git a/drivers/media/platform/intel/Kconfig b/drivers/media/platform/intel/Kconfig index 31e117e225a7..95e15c58cfef 100644 --- a/drivers/media/platform/intel/Kconfig +++ b/drivers/media/platform/intel/Kconfig @@ -94,6 +94,12 @@ config INTEL_IPU4_OX03A10 ---help--- "ox03a10 camera sensor" +config INTEL_IPU4_OV495 + bool "Compile platorm data for OV495" + depends on INTEL_IPU4_BXT_P_PDATA + ---help--- + "ov495 camera sensor" + config INTEL_IPU4_ICI_BXT_P_PDATA depends on VIDEO_INTEL_IPU && VIDEO_INTEL_ICI bool "Enable built in platform data for Broxton-P ICI driver" diff --git a/drivers/media/platform/intel/ipu4-bxt-p-pdata.c b/drivers/media/platform/intel/ipu4-bxt-p-pdata.c index de76065d6699..b7d0558bcae2 100644 --- a/drivers/media/platform/intel/ipu4-bxt-p-pdata.c +++ b/drivers/media/platform/intel/ipu4-bxt-p-pdata.c @@ -1203,6 +1203,29 @@ static struct crlmodule_platform_data ox03a10_pdata = { }; #endif +#ifdef CONFIG_INTEL_IPU4_OV495 +#define OV495_LANES 4 +#define OV495_I2C_PHY_ADDR 0x48 +#define OV495A_I2C_ADDRESS 0x30 +#define OV495B_I2C_ADDRESS 0x31 +#define OV495C_I2C_ADDRESS 0x32 +#define OV495D_I2C_ADDRESS 0x33 + +#define OV495A_SER_ADDRESS 0x58 +#define OV495B_SER_ADDRESS 0x59 +#define OV495C_SER_ADDRESS 0x5a +#define OV495D_SER_ADDRESS 0x5b + +static struct crlmodule_platform_data ov495_pdata = { + .lanes = OV495_LANES, + .ext_clk = 27000000, + .op_sys_clock = (uint64_t[]){ 87750000 }, + .module_name = "OV495", + .id_string = "0x51 0x49 0x56 0x4f", + .xshutdown = 1, +}; +#endif + #if IS_ENABLED(CONFIG_VIDEO_TI960) #define TI960_I2C_ADAPTER 2 #define TI960_I2C_ADAPTER_2 7 @@ -1245,6 +1268,56 @@ static struct ti960_subdev_info ti960_subdevs[] = { .suffix = 'b', }, #endif +#ifdef CONFIG_INTEL_IPU4_OV495 + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495A_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER, + .rx_port = 0, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495A_SER_ADDRESS, + .suffix = 'a', + }, + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495B_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER, + .rx_port = 1, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495B_SER_ADDRESS, + .suffix = 'b', + }, + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495C_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER, + .rx_port = 2, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495C_SER_ADDRESS, + .suffix = 'c', + }, + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495D_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER, + .rx_port = 3, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495D_SER_ADDRESS, + .suffix = 'd', + }, +#endif }; static struct ti960_subdev_info ti960_subdevs_2[] = { @@ -1274,6 +1347,56 @@ static struct ti960_subdev_info ti960_subdevs_2[] = { .suffix = 'f', }, #endif +#ifdef CONFIG_INTEL_IPU4_OV495 + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495A_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER_2, + .rx_port = 0, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495A_SER_ADDRESS, + .suffix = 'e', + }, + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495B_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER_2, + .rx_port = 1, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495B_SER_ADDRESS, + .suffix = 'f', + }, + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495C_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER_2, + .rx_port = 2, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495C_SER_ADDRESS, + .suffix = 'g', + }, + { + .board_info = { + .type = CRLMODULE_NAME, + .addr = OV495D_I2C_ADDRESS, + .platform_data = &ov495_pdata, + }, + .i2c_adapter_id = TI960_I2C_ADAPTER_2, + .rx_port = 3, + .phy_i2c_addr = OV495_I2C_PHY_ADDR, + .ser_alias = OV495D_SER_ADDRESS, + .suffix = 'h', + }, +#endif }; static struct ti960_pdata ti960_pdata = { -- https://clearlinux.org