From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Meng Wei Date: Tue, 27 Nov 2018 19:32:13 +0800 Subject: [PATCH] media: ov2775: update register setting Update ov2775 register setting, split exposure/gain out of main table Add standby register control Change-Id: Ib9b47a4e9af555af31c113af19e6744a45af7a30 Tracked-On: PKT-1624 Signed-off-by: mingdaxu Signed-off-by: Meng Wei --- .../i2c/crlmodule/crl_ov2775_configuration.h | 98 ++----------------- 1 file changed, 9 insertions(+), 89 deletions(-) diff --git a/drivers/media/i2c/crlmodule/crl_ov2775_configuration.h b/drivers/media/i2c/crlmodule/crl_ov2775_configuration.h index 917891371ebe..1734ed686765 100644 --- a/drivers/media/i2c/crlmodule/crl_ov2775_configuration.h +++ b/drivers/media/i2c/crlmodule/crl_ov2775_configuration.h @@ -16,7 +16,6 @@ static struct crl_register_write_rep ov2775_linear_hcg_30fps_mipi960_regset[] = { - {0x3013, CRL_REG_LEN_08BIT, 0x01}, {0x3000, CRL_REG_LEN_08BIT, 0x02}, {0x3001, CRL_REG_LEN_08BIT, 0x28}, {0x3002, CRL_REG_LEN_08BIT, 0x03}, @@ -31,7 +30,6 @@ static struct crl_register_write_rep {0x300e, CRL_REG_LEN_08BIT, 0x80}, {0x300f, CRL_REG_LEN_08BIT, 0x00}, {0x3012, CRL_REG_LEN_08BIT, 0x00}, - {0x3013, CRL_REG_LEN_08BIT, 0x00}, {0x3014, CRL_REG_LEN_08BIT, 0xc4}, {0x3015, CRL_REG_LEN_08BIT, 0x00}, {0x3017, CRL_REG_LEN_08BIT, 0x00}, @@ -106,18 +104,9 @@ static struct crl_register_write_rep {0x30ad, CRL_REG_LEN_08BIT, 0x80}, {0x30ae, CRL_REG_LEN_08BIT, 0x04}, {0x30af, CRL_REG_LEN_08BIT, 0x40}, - {0x30b0, CRL_REG_LEN_08BIT, 0x08}, - {0x30b1, CRL_REG_LEN_08BIT, 0x98}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x65}, {0x30b4, CRL_REG_LEN_08BIT, 0x00}, {0x30b5, CRL_REG_LEN_08BIT, 0x00}, - {0x30b6, CRL_REG_LEN_08BIT, 0x00}, - {0x30b7, CRL_REG_LEN_08BIT, 0x10}, - {0x30b8, CRL_REG_LEN_08BIT, 0x00}, - {0x30b9, CRL_REG_LEN_08BIT, 0x02}, {0x30ba, CRL_REG_LEN_08BIT, 0x10}, - {0x30bb, CRL_REG_LEN_08BIT, 0x00}, {0x30bc, CRL_REG_LEN_08BIT, 0x00}, {0x30bd, CRL_REG_LEN_08BIT, 0x03}, {0x30be, CRL_REG_LEN_08BIT, 0x5c}, @@ -212,12 +201,6 @@ static struct crl_register_write_rep {0x3157, CRL_REG_LEN_08BIT, 0x00}, {0x3158, CRL_REG_LEN_08BIT, 0x0f}, {0x3159, CRL_REG_LEN_08BIT, 0xff}, - {0x315a, CRL_REG_LEN_08BIT, 0x01}, - {0x315b, CRL_REG_LEN_08BIT, 0x00}, - {0x315c, CRL_REG_LEN_08BIT, 0x01}, - {0x315d, CRL_REG_LEN_08BIT, 0x00}, - {0x315e, CRL_REG_LEN_08BIT, 0x01}, - {0x315f, CRL_REG_LEN_08BIT, 0x00}, {0x3160, CRL_REG_LEN_08BIT, 0x01}, {0x3161, CRL_REG_LEN_08BIT, 0x00}, {0x3162, CRL_REG_LEN_08BIT, 0x01}, @@ -1802,26 +1785,17 @@ static struct crl_register_write_rep {0x3001, CRL_REG_LEN_08BIT, 0x32}, {0x3005, CRL_REG_LEN_08BIT, 0x13}, {0x3014, CRL_REG_LEN_08BIT, 0x44}, - {0x30b0, CRL_REG_LEN_08BIT, 0x1d}, - {0x30b1, CRL_REG_LEN_08BIT, 0xe2}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x60}, - {0x30b6, CRL_REG_LEN_08BIT, 0x04}, - {0x30b7, CRL_REG_LEN_08BIT, 0x5c}, {0x3196, CRL_REG_LEN_08BIT, 0x00}, {0x3197, CRL_REG_LEN_08BIT, 0x0a}, {0x3195, CRL_REG_LEN_08BIT, 0x04}, {0x31e3, CRL_REG_LEN_08BIT, 0x02}, {0x31e4, CRL_REG_LEN_08BIT, 0x10}, - {0x30bb, CRL_REG_LEN_08BIT, 0x40}, {0x3250, CRL_REG_LEN_08BIT, 0xf7}, - {0x3012, CRL_REG_LEN_08BIT, 0x01}, }; /* ov2775_1928x1088_linearlcg_30fps_mipi960_regset */ static struct crl_register_write_rep ov2775_linear_lcg_30fps_mipi960_regset[] = { - {0x3013, CRL_REG_LEN_08BIT, 0x01}, {0x3000, CRL_REG_LEN_08BIT, 0x02}, {0x3001, CRL_REG_LEN_08BIT, 0x28}, {0x3002, CRL_REG_LEN_08BIT, 0x03}, @@ -1836,7 +1810,6 @@ static struct crl_register_write_rep {0x300e, CRL_REG_LEN_08BIT, 0x80}, {0x300f, CRL_REG_LEN_08BIT, 0x00}, {0x3012, CRL_REG_LEN_08BIT, 0x00}, - {0x3013, CRL_REG_LEN_08BIT, 0x00}, {0x3014, CRL_REG_LEN_08BIT, 0xc4}, {0x3015, CRL_REG_LEN_08BIT, 0x00}, {0x3017, CRL_REG_LEN_08BIT, 0x00}, @@ -1911,18 +1884,9 @@ static struct crl_register_write_rep {0x30ad, CRL_REG_LEN_08BIT, 0x80}, {0x30ae, CRL_REG_LEN_08BIT, 0x04}, {0x30af, CRL_REG_LEN_08BIT, 0x40}, - {0x30b0, CRL_REG_LEN_08BIT, 0x08}, - {0x30b1, CRL_REG_LEN_08BIT, 0x98}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x65}, {0x30b4, CRL_REG_LEN_08BIT, 0x00}, {0x30b5, CRL_REG_LEN_08BIT, 0x00}, - {0x30b6, CRL_REG_LEN_08BIT, 0x00}, - {0x30b7, CRL_REG_LEN_08BIT, 0x10}, - {0x30b8, CRL_REG_LEN_08BIT, 0x00}, - {0x30b9, CRL_REG_LEN_08BIT, 0x02}, {0x30ba, CRL_REG_LEN_08BIT, 0x10}, - {0x30bb, CRL_REG_LEN_08BIT, 0x00}, {0x30bc, CRL_REG_LEN_08BIT, 0x00}, {0x30bd, CRL_REG_LEN_08BIT, 0x03}, {0x30be, CRL_REG_LEN_08BIT, 0x5c}, @@ -3607,24 +3571,16 @@ static struct crl_register_write_rep {0x3001, CRL_REG_LEN_08BIT, 0x32}, {0x3005, CRL_REG_LEN_08BIT, 0x13}, {0x3014, CRL_REG_LEN_08BIT, 0x44}, - {0x30b0, CRL_REG_LEN_08BIT, 0x1d}, - {0x30b1, CRL_REG_LEN_08BIT, 0xe2}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x60}, - {0x30b6, CRL_REG_LEN_08BIT, 0x04}, - {0x30b7, CRL_REG_LEN_08BIT, 0x5c}, {0x3196, CRL_REG_LEN_08BIT, 0x00}, {0x3197, CRL_REG_LEN_08BIT, 0x0a}, {0x3195, CRL_REG_LEN_08BIT, 0x04}, {0x31e3, CRL_REG_LEN_08BIT, 0x02}, {0x31e4, CRL_REG_LEN_08BIT, 0x10}, {0x3250, CRL_REG_LEN_08BIT, 0xf7}, - {0x3012, CRL_REG_LEN_08BIT, 0x01}, }; /* ov2775_1928x1088_2x12_30fps_mipi960_regset */ static struct crl_register_write_rep ov2775_2x12_30fps_mipi960_regset[] = { - {0x3013, CRL_REG_LEN_08BIT, 0x01}, {0x3000, CRL_REG_LEN_08BIT, 0x02}, {0x3001, CRL_REG_LEN_08BIT, 0x28}, {0x3002, CRL_REG_LEN_08BIT, 0x03}, @@ -3639,7 +3595,6 @@ static struct crl_register_write_rep ov2775_2x12_30fps_mipi960_regset[] = { {0x300e, CRL_REG_LEN_08BIT, 0x80}, {0x300f, CRL_REG_LEN_08BIT, 0x00}, {0x3012, CRL_REG_LEN_08BIT, 0x00}, - {0x3013, CRL_REG_LEN_08BIT, 0x00}, {0x3014, CRL_REG_LEN_08BIT, 0xc4}, {0x3015, CRL_REG_LEN_08BIT, 0x00}, {0x3017, CRL_REG_LEN_08BIT, 0x00}, @@ -3714,18 +3669,9 @@ static struct crl_register_write_rep ov2775_2x12_30fps_mipi960_regset[] = { {0x30ad, CRL_REG_LEN_08BIT, 0x80}, {0x30ae, CRL_REG_LEN_08BIT, 0x04}, {0x30af, CRL_REG_LEN_08BIT, 0x40}, - {0x30b0, CRL_REG_LEN_08BIT, 0x08}, - {0x30b1, CRL_REG_LEN_08BIT, 0x98}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x65}, {0x30b4, CRL_REG_LEN_08BIT, 0x00}, {0x30b5, CRL_REG_LEN_08BIT, 0x00}, - {0x30b6, CRL_REG_LEN_08BIT, 0x00}, - {0x30b7, CRL_REG_LEN_08BIT, 0x10}, - {0x30b8, CRL_REG_LEN_08BIT, 0x00}, - {0x30b9, CRL_REG_LEN_08BIT, 0x02}, {0x30ba, CRL_REG_LEN_08BIT, 0x10}, - {0x30bb, CRL_REG_LEN_08BIT, 0x00}, {0x30bc, CRL_REG_LEN_08BIT, 0x00}, {0x30bd, CRL_REG_LEN_08BIT, 0x03}, {0x30be, CRL_REG_LEN_08BIT, 0x5c}, @@ -5406,23 +5352,18 @@ static struct crl_register_write_rep ov2775_2x12_30fps_mipi960_regset[] = { {0x7891, CRL_REG_LEN_08BIT, 0x00}, {0x7892, CRL_REG_LEN_08BIT, 0x0f}, {0x7893, CRL_REG_LEN_08BIT, 0x00}, - {0x3001, CRL_REG_LEN_08BIT, 0x32}, - {0x3005, CRL_REG_LEN_08BIT, 0x13}, - {0x3014, CRL_REG_LEN_08BIT, 0x44}, {0x30a3, CRL_REG_LEN_08BIT, 0x00}, {0x30a7, CRL_REG_LEN_08BIT, 0x48}, {0x30ab, CRL_REG_LEN_08BIT, 0x04}, {0x30af, CRL_REG_LEN_08BIT, 0x40}, - {0x30b0, CRL_REG_LEN_08BIT, 0x3b}, - {0x30b1, CRL_REG_LEN_08BIT, 0x92}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x64}, + {0x3001, CRL_REG_LEN_08BIT, 0x32}, + {0x3005, CRL_REG_LEN_08BIT, 0x13}, + {0x3014, CRL_REG_LEN_08BIT, 0x44}, {0x3196, CRL_REG_LEN_08BIT, 0x00}, {0x3197, CRL_REG_LEN_08BIT, 0x00}, {0x3195, CRL_REG_LEN_08BIT, 0x04}, {0x31e3, CRL_REG_LEN_08BIT, 0x03}, {0x31e4, CRL_REG_LEN_08BIT, 0x13}, - {0x30bb, CRL_REG_LEN_08BIT, 0x1a}, {0x315a, CRL_REG_LEN_08BIT, 0x01}, {0x315b, CRL_REG_LEN_08BIT, 0x00}, {0x315c, CRL_REG_LEN_08BIT, 0x01}, @@ -5430,12 +5371,10 @@ static struct crl_register_write_rep ov2775_2x12_30fps_mipi960_regset[] = { {0x315e, CRL_REG_LEN_08BIT, 0x01}, {0x315f, CRL_REG_LEN_08BIT, 0x00}, {0x3250, CRL_REG_LEN_08BIT, 0xf7}, - {0x3012, CRL_REG_LEN_08BIT, 0x01}, }; /* ov2775_1928x1088_3x12_30fps_mipi960_regset */ static struct crl_register_write_rep ov2775_3x12_30fps_mipi960_regset[] = { - {0x3013, CRL_REG_LEN_08BIT, 0x01}, {0x3000, CRL_REG_LEN_08BIT, 0x02}, {0x3001, CRL_REG_LEN_08BIT, 0x28}, {0x3002, CRL_REG_LEN_08BIT, 0x03}, @@ -5449,8 +5388,6 @@ static struct crl_register_write_rep ov2775_3x12_30fps_mipi960_regset[] = { {0x300c, CRL_REG_LEN_08BIT, 0x6c}, {0x300e, CRL_REG_LEN_08BIT, 0x80}, {0x300f, CRL_REG_LEN_08BIT, 0x00}, - {0x3012, CRL_REG_LEN_08BIT, 0x00}, - {0x3013, CRL_REG_LEN_08BIT, 0x00}, {0x3014, CRL_REG_LEN_08BIT, 0xc4}, {0x3015, CRL_REG_LEN_08BIT, 0x00}, {0x3017, CRL_REG_LEN_08BIT, 0x00}, @@ -5525,18 +5462,9 @@ static struct crl_register_write_rep ov2775_3x12_30fps_mipi960_regset[] = { {0x30ad, CRL_REG_LEN_08BIT, 0x80}, {0x30ae, CRL_REG_LEN_08BIT, 0x04}, {0x30af, CRL_REG_LEN_08BIT, 0x40}, - {0x30b0, CRL_REG_LEN_08BIT, 0x08}, - {0x30b1, CRL_REG_LEN_08BIT, 0x98}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x65}, {0x30b4, CRL_REG_LEN_08BIT, 0x00}, {0x30b5, CRL_REG_LEN_08BIT, 0x00}, - {0x30b6, CRL_REG_LEN_08BIT, 0x00}, - {0x30b7, CRL_REG_LEN_08BIT, 0x10}, - {0x30b8, CRL_REG_LEN_08BIT, 0x00}, - {0x30b9, CRL_REG_LEN_08BIT, 0x02}, {0x30ba, CRL_REG_LEN_08BIT, 0x10}, - {0x30bb, CRL_REG_LEN_08BIT, 0x00}, {0x30bc, CRL_REG_LEN_08BIT, 0x00}, {0x30bd, CRL_REG_LEN_08BIT, 0x03}, {0x30be, CRL_REG_LEN_08BIT, 0x5c}, @@ -7214,23 +7142,18 @@ static struct crl_register_write_rep ov2775_3x12_30fps_mipi960_regset[] = { {0x7891, CRL_REG_LEN_08BIT, 0x00}, {0x7892, CRL_REG_LEN_08BIT, 0x0f}, {0x7893, CRL_REG_LEN_08BIT, 0x00}, - {0x3001, CRL_REG_LEN_08BIT, 0x23}, - {0x3005, CRL_REG_LEN_08BIT, 0x13}, - {0x3014, CRL_REG_LEN_08BIT, 0x44}, {0x30a3, CRL_REG_LEN_08BIT, 0x00}, {0x30a7, CRL_REG_LEN_08BIT, 0x48}, {0x30ab, CRL_REG_LEN_08BIT, 0x04}, {0x30af, CRL_REG_LEN_08BIT, 0x40}, - {0x30b0, CRL_REG_LEN_08BIT, 0x3e}, - {0x30b1, CRL_REG_LEN_08BIT, 0x9e}, - {0x30b2, CRL_REG_LEN_08BIT, 0x04}, - {0x30b3, CRL_REG_LEN_08BIT, 0x5a}, + {0x3001, CRL_REG_LEN_08BIT, 0x23}, + {0x3005, CRL_REG_LEN_08BIT, 0x13}, + {0x3014, CRL_REG_LEN_08BIT, 0x44}, {0x3196, CRL_REG_LEN_08BIT, 0x00}, {0x3197, CRL_REG_LEN_08BIT, 0x00}, {0x3195, CRL_REG_LEN_08BIT, 0x04}, {0x31e3, CRL_REG_LEN_08BIT, 0x03}, {0x31e4, CRL_REG_LEN_08BIT, 0x13}, - {0x30bb, CRL_REG_LEN_08BIT, 0x1a}, {0x315a, CRL_REG_LEN_08BIT, 0x01}, {0x315b, CRL_REG_LEN_08BIT, 0x00}, {0x315c, CRL_REG_LEN_08BIT, 0x01}, @@ -7238,15 +7161,12 @@ static struct crl_register_write_rep ov2775_3x12_30fps_mipi960_regset[] = { {0x315e, CRL_REG_LEN_08BIT, 0x01}, {0x315f, CRL_REG_LEN_08BIT, 0x00}, {0x3250, CRL_REG_LEN_08BIT, 0xf7}, - {0x3012, CRL_REG_LEN_08BIT, 0x01}, }; static struct crl_register_write_rep ov2775_powerup_standby_regset[] = { - { 0x3012, CRL_REG_LEN_08BIT, 0x00 } -}; - -struct crl_register_write_rep ov2775_poweroff_regset[] = { - { 0x3012, CRL_REG_LEN_08BIT, 0x00 } + { 0x3013, CRL_REG_LEN_08BIT, 0x01 }, + { 0x0000, CRL_REG_LEN_DELAY, 0x14 }, + { 0x3013, CRL_REG_LEN_08BIT, 0x00 }, }; static struct crl_register_write_rep ov2775_streamon_regs[] = { -- https://clearlinux.org