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update to PKT lts-v4.19.13-base-190117T091501Z 

Signed-off-by: Alek Du <alek.du@intel.com>
This commit is contained in:
Alek Du 2019-01-18 00:24:39 +00:00
parent 56e29b4ef7
commit f2142aee2e
12 changed files with 5749 additions and 4 deletions
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279
0872-drm-Add-per-plane-pixel-blend-mode-property.patch Normal file
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@ -0,0 +1,279 @@
From 702d282a946bc51096db62f3a100f19a35e4264e Mon Sep 17 00:00:00 2001
From: Lowry LI <lowry.li@arm.com>
Date: Thu, 23 Aug 2018 16:30:19 +0800
Subject: [PATCH 1/9] drm: Add per-plane pixel blend mode property
Pixel blend modes represent the alpha blending equation
selection, describing how the pixels from the current
plane are composited with the background.
Adds a pixel_blend_mode to drm_plane_state and a
blend_mode_property to drm_plane, and related support
functions.
Defines three blend modes in drm_blend.h.
Changes since v1:
- Moves the blending equation into the DOC comment
- Refines the comments of drm_plane_create_blend_mode_property to not
enumerate the #defines, but instead the string values
- Uses fg.* instead of pixel.* and plane_alpha instead of plane.alpha
Changes since v2:
- Refines the comments of drm_plane_create_blend_mode_property:
1) Puts the descriptions (after the ":") on a new line
2) Adds explaining why @supported_modes need PREMUL as default
Changes since v3:
- Refines drm_plane_create_blend_mode_property(). drm_property_add_enum()
can calculate the index itself just fine, so no point in having the
caller pass it in.
- Since the current DRM assumption is that alpha is premultiplied
as default, define DRM_MODE_BLEND_PREMULTI as 0 will be better.
- Refines some comments.
Changes since v4:
- Adds comments in drm_blend.h.
- Removes setting default value in drm_plane_create_blend_mode_property()
as it is already in __drm_atomic_helper_plane_reset().
- Fixes to use state->pixel_blend_mode instead of using
plane->state->pixel_blend_mode in reset function.
- Rebases on drm-misc-next.
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Lowry Li <lowry.li@arm.com>
Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/245734/
Tacked-On: OLINUX-3689
Signed-off-by: kimsehun <se.hun.kim@intel.com>
---
drivers/gpu/drm/drm_atomic.c | 4 +
drivers/gpu/drm/drm_atomic_helper.c | 1 +
drivers/gpu/drm/drm_blend.c | 123 ++++++++++++++++++++++++++++
include/drm/drm_blend.h | 6 ++
include/drm/drm_plane.h | 9 ++
5 files changed, 143 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index d3c3c65bf5b7..f2b173d07e41 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -910,6 +910,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane,
state->src_h = val;
} else if (property == plane->alpha_property) {
state->alpha = val;
+ } else if (property == plane->blend_mode_property) {
+ state->pixel_blend_mode = val;
} else if (property == plane->rotation_property) {
if (!is_power_of_2(val & DRM_MODE_ROTATE_MASK)) {
DRM_DEBUG_ATOMIC("[PLANE:%d:%s] bad rotation bitmask: 0x%llx\n",
@@ -985,6 +987,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = state->src_h;
} else if (property == plane->alpha_property) {
*val = state->alpha;
+ } else if (property == plane->blend_mode_property) {
+ *val = state->pixel_blend_mode;
} else if (property == plane->rotation_property) {
*val = state->rotation;
} else if (property == plane->zpos_property) {
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 824092d90cd0..a162880b2653 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -3586,6 +3586,7 @@ void drm_atomic_helper_plane_reset(struct drm_plane *plane)
/* Reset the alpha value to fully opaque if it matters */
if (plane->alpha_property)
plane->state->alpha = plane->alpha_property->values[1];
+ plane->state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
}
}
EXPORT_SYMBOL(drm_atomic_helper_plane_reset);
diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
index 183a7f6488c7..e0bbd1b004a5 100644
--- a/drivers/gpu/drm/drm_blend.c
+++ b/drivers/gpu/drm/drm_blend.c
@@ -107,6 +107,52 @@
* planes. Without this property the primary plane is always below the cursor
* plane, and ordering between all other planes is undefined.
*
+ * pixel blend mode:
+ * Pixel blend mode is set up with drm_plane_create_blend_mode_property().
+ * It adds a blend mode for alpha blending equation selection, describing
+ * how the pixels from the current plane are composited with the
+ * background.
+ *
+ * Three alpha blending equations are defined:
+ *
+ * "None":
+ * Blend formula that ignores the pixel alpha::
+ *
+ * out.rgb = plane_alpha * fg.rgb +
+ * (1 - plane_alpha) * bg.rgb
+ *
+ * "Pre-multiplied":
+ * Blend formula that assumes the pixel color values
+ * have been already pre-multiplied with the alpha
+ * channel values::
+ *
+ * out.rgb = plane_alpha * fg.rgb +
+ * (1 - (plane_alpha * fg.alpha)) * bg.rgb
+ *
+ * "Coverage":
+ * Blend formula that assumes the pixel color values have not
+ * been pre-multiplied and will do so when blending them to the
+ * background color values::
+ *
+ * out.rgb = plane_alpha * fg.alpha * fg.rgb +
+ * (1 - (plane_alpha * fg.alpha)) * bg.rgb
+ *
+ * Using the following symbols:
+ *
+ * "fg.rgb":
+ * Each of the RGB component values from the plane's pixel
+ * "fg.alpha":
+ * Alpha component value from the plane's pixel. If the plane's
+ * pixel format has no alpha component, then this is assumed to be
+ * 1.0. In these cases, this property has no effect, as all three
+ * equations become equivalent.
+ * "bg.rgb":
+ * Each of the RGB component values from the background
+ * "plane_alpha":
+ * Plane alpha value set by the plane "alpha" property. If the
+ * plane does not expose the "alpha" property, then this is
+ * assumed to be 1.0
+ *
* Note that all the property extensions described here apply either to the
* plane or the CRTC (e.g. for the background color, which currently is not
* exposed and assumed to be black).
@@ -480,3 +526,80 @@ int drm_atomic_normalize_zpos(struct drm_device *dev,
return 0;
}
EXPORT_SYMBOL(drm_atomic_normalize_zpos);
+
+/**
+ * drm_plane_create_blend_mode_property - create a new blend mode property
+ * @plane: drm plane
+ * @supported_modes: bitmask of supported modes, must include
+ * BIT(DRM_MODE_BLEND_PREMULTI). Current DRM assumption is
+ * that alpha is premultiplied, and old userspace can break if
+ * the property defaults to anything else.
+ *
+ * This creates a new property describing the blend mode.
+ *
+ * The property exposed to userspace is an enumeration property (see
+ * drm_property_create_enum()) called "pixel blend mode" and has the
+ * following enumeration values:
+ *
+ * "None":
+ * Blend formula that ignores the pixel alpha.
+ *
+ * "Pre-multiplied":
+ * Blend formula that assumes the pixel color values have been already
+ * pre-multiplied with the alpha channel values.
+ *
+ * "Coverage":
+ * Blend formula that assumes the pixel color values have not been
+ * pre-multiplied and will do so when blending them to the background color
+ * values.
+ *
+ * RETURNS:
+ * Zero for success or -errno
+ */
+int drm_plane_create_blend_mode_property(struct drm_plane *plane,
+ unsigned int supported_modes)
+{
+ struct drm_device *dev = plane->dev;
+ struct drm_property *prop;
+ static const struct drm_prop_enum_list props[] = {
+ { DRM_MODE_BLEND_PIXEL_NONE, "None" },
+ { DRM_MODE_BLEND_PREMULTI, "Pre-multiplied" },
+ { DRM_MODE_BLEND_COVERAGE, "Coverage" },
+ };
+ unsigned int valid_mode_mask = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE);
+ int i;
+
+ if (WARN_ON((supported_modes & ~valid_mode_mask) ||
+ ((supported_modes & BIT(DRM_MODE_BLEND_PREMULTI)) == 0)))
+ return -EINVAL;
+
+ prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
+ "pixel blend mode",
+ hweight32(supported_modes));
+ if (!prop)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(props); i++) {
+ int ret;
+
+ if (!(BIT(props[i].type) & supported_modes))
+ continue;
+
+ ret = drm_property_add_enum(prop, props[i].type,
+ props[i].name);
+
+ if (ret) {
+ drm_property_destroy(dev, prop);
+
+ return ret;
+ }
+ }
+
+ drm_object_attach_property(&plane->base, prop, DRM_MODE_BLEND_PREMULTI);
+ plane->blend_mode_property = prop;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_plane_create_blend_mode_property);
diff --git a/include/drm/drm_blend.h b/include/drm/drm_blend.h
index 74ba3e10b3a9..12912656ef08 100644
--- a/include/drm/drm_blend.h
+++ b/include/drm/drm_blend.h
@@ -27,6 +27,10 @@
#include <linux/ctype.h>
#include <drm/drm_mode.h>
+#define DRM_MODE_BLEND_PREMULTI 0
+#define DRM_MODE_BLEND_COVERAGE 1
+#define DRM_MODE_BLEND_PIXEL_NONE 2
+
struct drm_device;
struct drm_atomic_state;
struct drm_plane;
@@ -53,4 +57,6 @@ int drm_plane_create_zpos_immutable_property(struct drm_plane *plane,
unsigned int zpos);
int drm_atomic_normalize_zpos(struct drm_device *dev,
struct drm_atomic_state *state);
+int drm_plane_create_blend_mode_property(struct drm_plane *plane,
+ unsigned int supported_modes);
#endif
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 47d018e31bce..95c550a64ee8 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -117,6 +117,7 @@ struct drm_plane_state {
* details.
*/
u16 alpha;
+ uint16_t pixel_blend_mode;
/**
* @rotation:
@@ -673,6 +674,14 @@ struct drm_plane {
* drm_plane_create_rotation_property().
*/
struct drm_property *rotation_property;
+ /**
+ * @blend_mode_property:
+ * Optional "pixel blend mode" enum property for this plane.
+ * Blend mode property represents the alpha blending equation selection,
+ * describing how the pixels from the current plane are composited with
+ * the background.
+ */
+ struct drm_property *blend_mode_property;
/**
* @color_encoding_property:
--
2.17.1

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From b469be4bbee273ad7e74ebcfca06acaa9b8b4e92 Mon Sep 17 00:00:00 2001
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Date: Wed, 15 Aug 2018 12:34:05 +0200
Subject: [PATCH 2/9] drm/i915: Add plane alpha blending support, v2.
Add plane alpha blending support with the different blend modes.
This has been tested on a icl to show the correct results,
on earlier platforms small rounding errors cause issues. But this
already happens case with fully transparant or fully opaque RGB8888
fb's.
The recommended HW workaround is to disable alpha blending when the
plane alpha is 0 (transparant, hide plane) or 0xff (opaque, disable blending).
This is easy to implement on any platform, so just do that.
The tests for userspace are also available, and pass on gen11.
Changes since v1:
- Change mistaken < 0xff0 to 0xff00.
- Only set PLANE_KEYMSK_ALPHA_ENABLE when plane alpha < 0xff00, ignore blend mode.
- Rework disabling FBC when per pixel alpha is used.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
[mlankhorst: Change MISSING_CASE default to explicit alpha disable (mattrope)]
Link: https://patchwork.freedesktop.org/patch/msgid/20180815103405.22679-1-maarten.lankhorst@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tacked-On: OLINUX-3689
Signed-off-by: kimsehun <se.hun.kim@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 52 +++++++++++++++++++---------
drivers/gpu/drm/i915/intel_fbc.c | 8 +++++
drivers/gpu/drm/i915/intel_sprite.c | 23 ++++++++++--
5 files changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0633ea208a9..fb6539653859 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -558,6 +558,8 @@ struct intel_fbc {
int adjusted_y;
int y;
+
+ uint16_t pixel_blend_mode;
} plane;
struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0297014630a5..c69f6278720a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,8 +6569,10 @@ enum {
#define _PLANE_KEYVAL_2_A 0x70294
#define _PLANE_KEYMSK_1_A 0x70198
#define _PLANE_KEYMSK_2_A 0x70298
+#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
+#define PLANE_KEYMAX_ALPHA_SHIFT 24
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 223cda4b380c..d6b368e39ea8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3183,6 +3183,10 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
+ /* HW only has 8 bits pixel precision, disable plane if invisible */
+ if (!(plane_state->base.alpha >> 8))
+ plane_state->base.visible = false;
+
if (!plane_state->base.visible)
return 0;
@@ -3528,29 +3532,38 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return 0;
}
-/*
- * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
- * to be already pre-multiplied. We need to add a knob (or a different
- * DRM_FORMAT) for user-space to configure that.
- */
-static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
+static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
{
- switch (pixel_format) {
- case DRM_FORMAT_ABGR8888:
- case DRM_FORMAT_ARGB8888:
+ if (!plane_state->base.fb->format->has_alpha)
+ return PLANE_CTL_ALPHA_DISABLE;
+
+ switch (plane_state->base.pixel_blend_mode) {
+ case DRM_MODE_BLEND_PIXEL_NONE:
+ return PLANE_CTL_ALPHA_DISABLE;
+ case DRM_MODE_BLEND_PREMULTI:
return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+ case DRM_MODE_BLEND_COVERAGE:
+ return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
default:
+ MISSING_CASE(plane_state->base.pixel_blend_mode);
return PLANE_CTL_ALPHA_DISABLE;
}
}
-static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
+static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
{
- switch (pixel_format) {
- case DRM_FORMAT_ABGR8888:
- case DRM_FORMAT_ARGB8888:
+ if (!plane_state->base.fb->format->has_alpha)
+ return PLANE_COLOR_ALPHA_DISABLE;
+
+ switch (plane_state->base.pixel_blend_mode) {
+ case DRM_MODE_BLEND_PIXEL_NONE:
+ return PLANE_COLOR_ALPHA_DISABLE;
+ case DRM_MODE_BLEND_PREMULTI:
return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
+ case DRM_MODE_BLEND_COVERAGE:
+ return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
default:
+ MISSING_CASE(plane_state->base.pixel_blend_mode);
return PLANE_COLOR_ALPHA_DISABLE;
}
}
@@ -3627,7 +3640,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
plane_ctl = PLANE_CTL_ENABLE;
if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
- plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
+ plane_ctl |= skl_plane_ctl_alpha(plane_state);
plane_ctl |=
PLANE_CTL_PIPE_GAMMA_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3669,7 +3682,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
}
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
- plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+ plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv) {
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
@@ -13878,7 +13891,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
DRM_ERROR("Failed to create decryption property\n");
}
- if (INTEL_GEN(dev_priv) >= 9)
+ if (INTEL_GEN(dev_priv) >= 9) {
drm_plane_create_color_properties(&primary->base,
BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709),
@@ -13887,6 +13900,13 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
+ drm_plane_create_alpha_property(&primary->base);
+ drm_plane_create_blend_mode_property(&primary->base,
+ BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE));
+ }
+
drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
return primary;
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 01d1d2088f04..c07d69f22e40 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -674,6 +674,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->plane.adjusted_y = plane_state->main.y;
cache->plane.y = plane_state->base.src.y1 >> 16;
+ cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
+
if (!cache->plane.visible)
return;
@@ -748,6 +750,12 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
+ if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
+ cache->fb.format->has_alpha) {
+ fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
+ return false;
+ }
+
/* WaFbcExceedCdClockThreshold:hsw,bdw */
if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2c0cc897c41e..74d594232843 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -319,6 +319,7 @@ skl_update_plane(struct intel_plane *plane,
uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
uint32_t val;
unsigned long irqflags;
+ u32 keymsk = 0, keymax = 0;
#if IS_ENABLED(CONFIG_DRM_I915_GVT)
if (dev_priv->gvt &&
@@ -345,10 +346,19 @@ skl_update_plane(struct intel_plane *plane,
if (key->flags) {
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
- I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
- I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
+
+ keymax |= key->max_value & 0xffffff;
+ keymsk |= key->channel_mask & 0x3ffffff;
}
+ keymax |= (plane_state->base.alpha >> 8) << PLANE_KEYMAX_ALPHA_SHIFT;
+
+ if (plane_state->base.alpha < 0xff00)
+ keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
+
+ I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
+ I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
+
I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
@@ -1745,6 +1755,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
+ if (INTEL_GEN(dev_priv) >= 9) {
+ drm_plane_create_alpha_property(&intel_plane->base);
+
+ drm_plane_create_blend_mode_property(&intel_plane->base,
+ BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE));
+ }
+
drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
return intel_plane;
--
2.17.1

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@ -0,0 +1,195 @@
From 371b542556f3a007d5213b17a63c5d7960ca699d Mon Sep 17 00:00:00 2001
From: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Date: Thu, 10 Jan 2019 16:18:59 -0800
Subject: [PATCH 3/9] igb_avb: Fix invalid memory access after S3
suspend/resume cycles
Manually (igb_avb is based on the stable igb driver, so applying the
patches from upstream was resulting in a lot of conflicts) backport
the following patches:
commit 89dbefb213a0b3e53fe1a99ec9c1a230aad5f404
From: Aaron Sierra <asierra@xes-inc.com>
Date: Thu, 31 Oct 2013 00:32:34 +0000
commit 75009b3a88cd8f56315eb4ced296ee2f060cf946
From: Peter Senna Tschudin <peter.senna@gmail.com>
Date: Thu, 20 Mar 2014 03:31:08 +0000
commit 73bf8048d7c86a20a59d427e55deb1a778e94df7
From: Jarod Wilson <jarod@redhat.com>
Date: Thu, 10 Sep 2015 15:37:50 -0400
commit 7b06a6909555ffb0140733cc4420222604140b27
From: Jarod Wilson <jarod@redhat.com>
Date: Mon, 19 Oct 2015 11:52:04 -0400
commit 629823b872402451b42462414da08dddd0e2c93d
From: Cao jin <caoj.fnst@cn.fujitsu.com>
Date: Tue, 8 Nov 2016 15:06:20 +0800
commit 69b97cf6dbce7403845a28bbc75d57f5be7b12ac
From: Guilherme G Piccoli <gpiccoli@linux.vnet.ibm.com>
Date: Thu, 10 Nov 2016 16:46:43 -0200
Also, having only one commit makes it easier to revert, if necessary.
In theory, only the last two commits were needed, but because of
changes in how PCI addresses are mapped in igb, it was best to
backport those other commits that make igb use more modern APIs when
mapping/unmapping PCI addresses.
This should fix the following crash:
[ 5271.634522] PM: Restoring platform NVS memory
[ 5271.646807] ACPI: Waking up from system sleep state S3
[ 5271.892182] intel-ipu4 0000:00:03.0: IPU in secure mode
[ 5271.893875] igb_avb 0000:02:00.0 ens4: PCIe link lost, device now detached
[ 5271.894735] [drm] HuC: Loaded firmware i915/bxt_huc_ver01_07_1398.bin (version 1.7)
[ 5271.900810] [drm] GuC: Loaded firmware i915/bxt_guc_ver9_29.bin (version 9.29)
[ 5271.906584] i915 0000:00:02.0: GuC firmware version 9.29
[ 5271.906908] i915 0000:00:02.0: GuC submission disabled
[ 5271.907204] i915 0000:00:02.0: HuC enabled
[ 5273.028933] BUG: unable to handle kernel paging request at 0000000000003818
[ 5273.032434] PGD 0 P4D 0
[ 5273.035664] Oops: 0002 [#1] PREEMPT SMP
[ 5273.038954] CPU: 0 PID: 938 Comm: kworker/u8:29 Tainted: G U WC 4.19.8-1812241100.iot-lts2018-sos #1
[ 5273.042592] Workqueue: events_unbound async_run_entry_fn
[ 5273.045932] RIP: 0010:igb_configure_tx_ring+0x13f/0x230 [igb_avb]
[ 5273.049309] Code: c2 10 38 00 00 48 98 48 01 c1 48 63 c2 49 89 4e 30 49 8b b5 58 04 00 00 48 85 f6 74 0b 48 01 f0 31 d2 89 10 49 8b 4e 30 31 c0 <89> 01 41 8b 85 6c 05 00 00 b9 14 01 04 02 83 f8 05 74 0e 83 f8 02
[ 5273.056633] RSP: 0018:ffff9d380f917cc0 EFLAGS: 00010246
[ 5273.060068] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000003818
[ 5273.063613] RDX: 0000000000003810 RSI: 0000000000000000 RDI: 00000000ffffffff
[ 5273.067080] RBP: ffff9d380f917ce8 R08: 000000000000007f R09: 000000000000007f
[ 5273.162184] R10: 0000000000005c80 R11: 0000000000000000 R12: 0000000000000000
[ 5273.165614] R13: ffff9d3a637b4940 R14: ffff9d3a5c459a40 R15: 000000027c01c000
[ 5273.169050] FS: 0000000000000000(0000) GS:ffff9d3a73a00000(0000) knlGS:0000000000000000
[ 5273.172554] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 5273.175906] CR2: 0000000000003818 CR3: 0000000003f04000 CR4: 00000000003406f0
[ 5273.179338] Call Trace:
[ 5273.182445] igb_configure+0x1ae/0x460 [igb_avb]
[ 5273.185648] __igb_open+0x7e/0x560 [igb_avb]
[ 5273.245233] igb_resume+0x10b/0x140 [igb_avb]
[ 5273.248388] pci_pm_resume+0x71/0xd0
[ 5273.254596] dpm_run_callback+0x66/0x190
[ 5273.257614] device_resume+0xc8/0x2a0
[ 5273.260570] async_resume+0x1d/0x30
[ 5273.263509] async_run_entry_fn+0x3e/0x170
Change-Id: I3c21a8cf1450e996509505a9d35bda3a4a4864d9
Tracked-on: PKT-1646
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
---
drivers/staging/igb_avb/igb.h | 2 ++
drivers/staging/igb_avb/igb_main.c | 25 +++++++++++++++----------
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/igb_avb/igb.h b/drivers/staging/igb_avb/igb.h
index c8bbf307f908..4482f7407955 100644
--- a/drivers/staging/igb_avb/igb.h
+++ b/drivers/staging/igb_avb/igb.h
@@ -562,6 +562,8 @@ struct igb_adapter {
u16 link_duplex;
u8 port_num;
+ u8 __iomem *io_addr; /* Mainly for iounmap use */
+
/* Interrupt Throttle Rate */
u32 rx_itr_setting;
u32 tx_itr_setting;
diff --git a/drivers/staging/igb_avb/igb_main.c b/drivers/staging/igb_avb/igb_main.c
index 8d772cfbe397..08dbf5d5a481 100644
--- a/drivers/staging/igb_avb/igb_main.c
+++ b/drivers/staging/igb_avb/igb_main.c
@@ -707,7 +707,6 @@ static void igb_configure_msix(struct igb_adapter *adapter)
static int igb_request_msix(struct igb_adapter *adapter)
{
struct net_device *netdev = adapter->netdev;
- struct e1000_hw *hw = &adapter->hw;
int i, err = 0, vector = 0, free_vector = 0;
err = request_irq(adapter->msix_entries[vector].vector,
@@ -720,7 +719,7 @@ static int igb_request_msix(struct igb_adapter *adapter)
vector++;
- q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
+ q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
if (q_vector->rx.ring && q_vector->tx.ring)
sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
@@ -1198,7 +1197,7 @@ static int igb_alloc_q_vector(struct igb_adapter *adapter,
q_vector->tx.work_limit = adapter->tx_work_limit;
/* initialize ITR configuration */
- q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
+ q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
q_vector->itr_val = IGB_START_ITR;
/* initialize pointer to rings */
@@ -2720,10 +2719,11 @@ static int igb_probe(struct pci_dev *pdev,
goto err_ioremap;
#endif
err = -EIO;
- hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
- pci_resource_len(pdev, 0));
- if (!hw->hw_addr)
+ adapter->io_addr = pci_iomap(pdev, 0, 0);
+ if (!adapter->io_addr)
goto err_ioremap;
+ /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
+ hw->hw_addr = adapter->io_addr;
#ifdef HAVE_NET_DEVICE_OPS
netdev->netdev_ops = &igb_netdev_ops;
@@ -3138,7 +3138,7 @@ static int igb_probe(struct pci_dev *pdev,
err_sw_init:
igb_clear_interrupt_scheme(adapter);
igb_reset_sriov_capability(adapter);
- iounmap(hw->hw_addr);
+ pci_iounmap(pdev, adapter->io_addr);
err_ioremap:
free_netdev(netdev);
err_alloc_etherdev:
@@ -3221,7 +3221,7 @@ static void igb_remove(struct pci_dev *pdev)
igb_clear_interrupt_scheme(adapter);
- iounmap(hw->hw_addr);
+ pci_iounmap(pdev, adapter->io_addr);
if (hw->flash_address)
iounmap(hw->flash_address);
pci_release_selected_regions(pdev,
@@ -3620,7 +3620,7 @@ void igb_configure_tx_ring(struct igb_adapter *adapter,
tdba & 0x00000000ffffffffULL);
E1000_WRITE_REG(hw, E1000_TDBAH(reg_idx), tdba >> 32);
- ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
+ ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
E1000_WRITE_REG(hw, E1000_TDH(reg_idx), 0);
writel(0, ring->tail);
@@ -4051,7 +4051,7 @@ void igb_configure_rx_ring(struct igb_adapter *adapter,
ring->count * sizeof(union e1000_adv_rx_desc));
/* initialize head and tail */
- ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
+ ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
E1000_WRITE_REG(hw, E1000_RDH(reg_idx), 0);
writel(0, ring->tail);
@@ -9638,6 +9638,11 @@ static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
+ /* In case of PCI error, adapter lose its HW address
+ * so we should re-assign it here.
+ */
+ hw->hw_addr = adapter->io_addr;
+
schedule_work(&adapter->reset_task);
E1000_WRITE_REG(hw, E1000_WUS, ~0);
result = PCI_ERS_RESULT_RECOVERED;
--
2.17.1

657
0875-drm-i915-Introduce-initial-mode-setting.patch Normal file
View File

@ -0,0 +1,657 @@
From c772e36d6fc7bc2b8dc90ac1652446ce4bd51770 Mon Sep 17 00:00:00 2001
From: Bob Paauwe <bob.j.paauwe@intel.com>
Date: Fri, 22 Apr 2016 16:43:18 -0700
Subject: [PATCH 4/9] drm/i915: Introduce initial mode setting
For very specific use cases it may be desirable to have the kernel
driver do an initial mode set and/or splash screen type display without
having to enable a framebuffer console.
A primary goal for this feature is to have the display lit up as soon
as possible. A non-goal is the ability to detect and adapt to the
display configurations. In other words, the display configuration will
be a known/fixed configuration. In addition, it is expected that the
EDID information will be present and optimized so mode list creation
and traversal time is minimized.
Add a new module parameter that replaces the normal fbdev initialization
with a new initial mode set. When the parameter is off, follow the normal
program flow and (if configured) initialize fbdev and a framebuffer
console. When the parameter is on, do an atomic mode set with everything
off (no crtc's enabled).
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: James Xiong <james.xiong@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Ported to linux-lts-2018 kernel base only.
Ran checkpatch.pl and fixed errors with new file.
Tracked-on:OLINUX-3112
Change-Id: I2f26670e337ad85c90ada0c15aca46d2e51bccb2
Signed-off-by: Daniel Charles <daniel.charles@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/i915_drv.c | 21 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_params.c | 3 +
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_initial_modeset.c | 489 +++++++++++++++++++
6 files changed, 519 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_initial_modeset.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 517620bcbadd..c70a494bb213 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -190,4 +190,7 @@ endif
# LPE Audio for VLV and CHT
i915-y += intel_lpe_audio.o
+# initial modeset
+i915-y += intel_initial_modeset.o
+
obj-$(CONFIG_DRM_I915) += i915.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5c25a82265b1..c7f4f94fd49b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -690,9 +690,11 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (INTEL_INFO(dev_priv)->num_pipes == 0)
return 0;
- ret = intel_fbdev_init(dev);
- if (ret)
- goto cleanup_gem;
+ if (!i915_modparams.enable_initial_modeset) {
+ ret = intel_fbdev_init(dev);
+ if (ret)
+ goto cleanup_gem;
+ }
/* Only enable hotplug handling once the fbdev is fully set up. */
intel_hpd_init(dev_priv);
@@ -1286,7 +1288,10 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
* irqs are fully enabled. We do it last so that the async config
* cannot run before the connectors are registered.
*/
- intel_fbdev_initial_config_async(dev);
+ if (i915_modparams.enable_initial_modeset)
+ intel_initial_mode_config_init(dev);
+ else
+ intel_fbdev_initial_config_async(dev);
/*
* We need to coordinate the hotplugs with the asynchronous fbdev
@@ -1475,6 +1480,11 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_unregister(dev_priv);
+ if (!i915_modparams.enable_initial_modeset)
+ intel_fbdev_fini(dev_priv);
+ else
+ intel_initial_mode_config_fini(dev);
+
if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
@@ -1544,7 +1554,8 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
*/
static void i915_driver_lastclose(struct drm_device *dev)
{
- intel_fbdev_restore_mode(dev);
+ if (!i915_modparams.enable_initial_modeset)
+ intel_fbdev_restore_mode(dev);
vga_switcheroo_process_delayed_switch();
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0633ea208a9..8a4fb73727fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1774,6 +1774,8 @@ struct drm_i915_private {
struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif
+ struct work_struct initial_modeset_work;
+
/* dpll and cdclk state is protected by connection_mutex */
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
@@ -2762,6 +2764,11 @@ extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
+
+/* initial modesetting support */
+extern void intel_initial_mode_config_init(struct drm_device *dev);
+extern void intel_initial_mode_config_fini(struct drm_device *dev);
+
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index e594fd3cf6c9..c588edb4a41d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -178,6 +178,9 @@ i915_param_named(gvt_workload_priority, int, 0600,
"Set GVT-g workload priority, (range: (-1023, 1023), default: 0, "
"more positive value means higher priority).");
+i915_param_named(enable_initial_modeset, bool, 0400,
+ "Do initial modeset (default : false)");
+
i915_param_named(domain_scaler_owner, int, 0400,
"scaler owners for each domain and for each pipe ids can be from 0-F");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index a0d1d7e7a3ac..9df42e8d99c0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -76,6 +76,7 @@ struct drm_printer;
| PVMMIO_PLANE_WM_UPDATE | PVMMIO_PPGTT_UPDATE \
| PVMMIO_GGTT_UPDATE ) \
param(int, gvt_workload_priority, 0) \
+ param(bool, enable_initial_modeset, false) \
param(bool, enable_gvt, false) \
param(bool, enable_conformance_check, true)
diff --git a/drivers/gpu/drm/i915/intel_initial_modeset.c b/drivers/gpu/drm/i915/intel_initial_modeset.c
new file mode 100644
index 000000000000..4a3a6e7b0f9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_initial_modeset.c
@@ -0,0 +1,489 @@
+/*
+ *
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions: *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+ * DOC: Boot-time mode setting.
+ *
+ * There exists a use case where the kernel graphics needs to be initialized
+ * with a valid display configuration with full display pipeline programming
+ * in place before user space is initialized and without a fbdev & fb console.
+ *
+ * The primary motivation is to allow early user space applications to
+ * display a frame (or frames) as soon as possible after user space starts.
+ * Eliminating the time it takes userspace to program the display configuration
+ * benefits this use case.
+ *
+ * By doing all the display programming in the kernel, it can be done in
+ * parallel with other kernel startup tasks without adding significant
+ * elapshed time before user space starts.
+ */
+
+#include "intel_drv.h"
+#include "i915_drv.h"
+
+static inline struct drm_encoder *get_encoder(struct drm_connector *connector)
+{
+ struct intel_encoder *encoder;
+
+ encoder = intel_attached_encoder(connector);
+
+ return &encoder->base;
+}
+
+/*
+ * This makes use of the video= kernel command line to determine what
+ * connectors to configure. See Documentation/fb/modedb.txt for details
+ * on the format. There are 3 specific cases that are used:
+ *
+ * 1) video=<connector>
+ * - assume monitor is connected, use EDID preferred mode
+ * 2) video=<connector:e>
+ * - use regardless of monitor connected, use EDID preferred mode
+ * 3) video=<connector:xres x yres @ refresh e
+ * - use regardless of monitor connected and use specified mode.
+ */
+static bool use_connector(struct drm_connector *connector)
+{
+ char *option = NULL;
+ struct drm_cmdline_mode *cl_mode = &connector->cmdline_mode;
+
+ fb_get_options(connector->name, &option);
+ if (option) {
+ switch (connector->force) {
+
+ case DRM_FORCE_OFF:
+ return false;
+ case DRM_FORCE_ON:
+ case DRM_FORCE_ON_DIGITAL:
+ return true;
+ case DRM_FORCE_UNSPECIFIED:
+ break;
+ }
+
+ connector->status = connector->funcs->detect(connector, true);
+ if (connector->status != connector_status_connected) {
+ connector->force = cl_mode->force;
+ connector->status = connector_status_connected;
+ }
+ return true;
+ }
+
+ return false;
+}
+
+static bool attach_crtc(struct drm_device *dev, struct drm_encoder *encoder,
+ uint32_t *used_crtcs)
+{
+ struct drm_crtc *possible_crtc;
+
+ if (encoder->crtc != NULL &&
+ !(*used_crtcs & drm_crtc_mask(encoder->crtc))) {
+ *used_crtcs |= drm_crtc_mask(encoder->crtc);
+ return true;
+ }
+
+ drm_for_each_crtc(possible_crtc, dev) {
+ if (!(encoder->possible_crtcs & drm_crtc_mask(possible_crtc))
+ || (*used_crtcs & drm_crtc_mask(possible_crtc)))
+ continue;
+ *used_crtcs |= drm_crtc_mask(possible_crtc);
+ encoder->crtc = possible_crtc;
+ return true;
+ }
+
+ return false;
+}
+
+static struct drm_display_mode *get_modeline(struct drm_i915_private *dev_priv,
+ struct drm_connector *connector,
+ int width, int height)
+{
+ struct drm_display_mode *mode;
+ struct drm_cmdline_mode *cl_mode = &connector->cmdline_mode;
+
+ /*
+ * fill_modes() takes a bit of time but is necessary.
+ * It is reading the EDID (or loading the EDID firmware blob
+ * and building the connector mode list. The time can be
+ * minimized by using a small EDID blob built into the kernel.
+ */
+
+ connector->funcs->fill_modes(connector, width, height);
+
+ /*
+ * Search the mode list. If a mode was specified using the
+ * video= command line, use that. Otherwise look for the
+ * preferred mode.
+ *
+ * <connector:><xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
+ */
+ list_for_each_entry(mode, &connector->modes, head) {
+ if (cl_mode && cl_mode->specified &&
+ cl_mode->refresh_specified) {
+ if (mode->hdisplay == cl_mode->xres &&
+ mode->vdisplay == cl_mode->yres &&
+ mode->vrefresh == cl_mode->refresh)
+ return mode;
+ } else if (cl_mode && cl_mode->specified) {
+ if (mode->hdisplay == cl_mode->xres &&
+ mode->vdisplay == cl_mode->yres)
+ return mode;
+ } else {
+ if (mode->type & DRM_MODE_TYPE_PREFERRED)
+ return mode;
+ }
+ }
+
+ DRM_ERROR("Failed to find a valid mode.\n");
+ return NULL;
+}
+
+static int update_crtc_state(struct drm_atomic_state *state,
+ struct drm_display_mode *mode,
+ struct drm_crtc *crtc)
+{
+ struct drm_crtc_state *crtc_state;
+ int ret;
+
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ ret = drm_atomic_set_mode_for_crtc(crtc_state, mode);
+ if (ret) {
+ crtc_state->active = false;
+ return ret;
+ }
+
+ crtc_state->active = true;
+
+ if (!IS_GEN9(to_i915(state->dev)))
+ return 0;
+
+ WARN_ON(ret);
+
+ return 0;
+}
+
+static int update_connector_state(struct drm_atomic_state *state,
+ struct drm_connector *connector,
+ struct drm_crtc *crtc)
+{
+ struct drm_connector_state *conn_state;
+ int ret;
+
+ conn_state = drm_atomic_get_connector_state(state, connector);
+ if (IS_ERR(conn_state)) {
+ DRM_DEBUG_KMS("failed to get connector %s state\n",
+ connector->name);
+ return PTR_ERR(conn_state);
+ }
+
+ ret = drm_atomic_set_crtc_for_connector(conn_state, crtc);
+ if (ret) {
+ DRM_DEBUG_KMS("failed to set crtc for connector\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int update_primary_plane_state(struct drm_atomic_state *state,
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_framebuffer *fb)
+{
+ int hdisplay, vdisplay;
+ struct drm_plane_state *primary_state;
+ int ret;
+
+ primary_state = drm_atomic_get_plane_state(state, crtc->primary);
+ ret = drm_atomic_set_crtc_for_plane(primary_state, crtc);
+ if (ret)
+ return ret;
+ drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
+ drm_atomic_set_fb_for_plane(primary_state, fb);
+ primary_state->crtc_x = 0;
+ primary_state->crtc_y = 0;
+ primary_state->crtc_w = hdisplay;
+ primary_state->crtc_h = vdisplay;
+ primary_state->src_x = 0 << 16;
+ primary_state->src_y = 0 << 16;
+ primary_state->src_w = hdisplay << 16;
+ primary_state->src_h = vdisplay << 16;
+ primary_state->rotation = DRM_MODE_ROTATE_0;
+
+ return 0;
+}
+
+static int update_atomic_state(struct drm_device *dev,
+ struct drm_atomic_state *state,
+ struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct drm_framebuffer *fb = NULL;
+ struct drm_crtc *crtc;
+ int ret;
+
+ if (get_encoder(connector))
+ crtc = get_encoder(connector)->crtc;
+ else
+ return -EINVAL;
+
+ ret = update_crtc_state(state, mode, crtc);
+ if (ret)
+ return ret;
+
+ /* attach connector to atomic state */
+ ret = update_connector_state(state, connector, crtc);
+ if (ret)
+ return ret;
+
+ /* Set up primary plane if a framebuffer is allocated */
+ if (fb) {
+ ret = update_primary_plane_state(state, crtc, mode, fb);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+
+static int disable_planes(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_plane *plane;
+ int ret;
+
+ drm_for_each_plane(plane, dev) {
+ struct drm_plane_state *plane_state;
+
+ plane->old_fb = plane->fb;
+
+ plane_state = drm_atomic_get_plane_state(state, plane);
+ if (IS_ERR(plane_state)) {
+ return PTR_ERR(plane_state);
+ }
+
+ ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
+ if (ret != 0)
+ return ret;
+
+ drm_atomic_set_fb_for_plane(plane_state, NULL);
+ }
+
+ return 0;
+}
+
+
+/*
+ * The modeset_config is scheduled to run via an async
+ * schedule call from the main driver load.
+ */
+static void modeset_config_fn(struct work_struct *work)
+{
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), initial_modeset_work);
+ struct drm_device *dev = &dev_priv->drm;
+ struct drm_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_atomic_state *state;
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_plane *plane;
+ int ret;
+ bool found = false;
+ uint32_t used_crtcs = 0;
+ struct drm_display_mode *connector_mode[20];
+ struct drm_encoder *encoder;
+ struct drm_display_mode *mode;
+
+ memset(connector_mode, 0, sizeof(connector_mode));
+ mutex_lock(&dev->mode_config.mutex);
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(connector, &conn_iter) {
+ if (use_connector(connector)) {
+ encoder = get_encoder(connector);
+ if (!encoder)
+ continue;
+ if (!attach_crtc(dev, encoder, &used_crtcs))
+ continue;
+ mode = get_modeline(dev_priv, connector,
+ dev->mode_config.max_width,
+ dev->mode_config.max_height);
+ if (mode) {
+ found = true;
+ WARN_ON(connector->index >= 20);
+ connector_mode[connector->index] = mode;
+ }
+ }
+ }
+ drm_connector_list_iter_end(&conn_iter);
+ if (!found) {
+ used_crtcs = 0;
+ /* Try to detect attached connectors */
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(connector, &conn_iter) {
+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+ if (connector->funcs && connector->funcs->detect)
+ connector->status = connector->funcs->detect(connector,
+ true);
+ else if (connector->helper_private && connector->helper_private->detect_ctx)
+ connector->status = connector->helper_private->detect_ctx(connector,
+ NULL, true);
+ drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ if (connector->status == connector_status_connected) {
+ encoder = get_encoder(connector);
+ if (!encoder)
+ continue;
+ if (!attach_crtc(dev, encoder, &used_crtcs))
+ continue;
+ mode = get_modeline(dev_priv, connector,
+ dev->mode_config.max_width,
+ dev->mode_config.max_height);
+ if (mode) {
+ found = true;
+ WARN_ON(connector->index >= 20);
+ connector_mode[connector->index] = mode;
+ }
+ }
+ }
+ drm_connector_list_iter_end(&conn_iter);
+ }
+ mutex_unlock(&dev->mode_config.mutex);
+
+ if (!found)
+ return;
+
+ state = drm_atomic_state_alloc(dev);
+ if (!state)
+ return;
+
+ mutex_lock(&dev->mode_config.mutex);
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state->acquire_ctx = &ctx;
+retry:
+ ret = drm_modeset_lock_all_ctx(dev, &ctx);
+ if (ret == -EDEADLK) {
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ } else if (ret) {
+ goto out;
+ }
+
+ ret = disable_planes(dev, state);
+ if (ret)
+ goto fail;
+
+ /*
+ * For each connector that we want to set up, update the atomic
+ * state to include the connector and crtc mode.
+ */
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(connector, &conn_iter) {
+ if (connector_mode[connector->index]) {
+ ret = update_atomic_state(dev, state, connector,
+ connector_mode[connector->index]);
+ if (ret)
+ goto fail;
+ }
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ ret = drm_atomic_commit(state);
+ if (ret)
+ goto fail;
+ goto out;
+
+fail:
+ if (ret == -EDEADLK) {
+ DRM_DEBUG_KMS("modeset commit deadlock, retry...\n");
+ drm_modeset_backoff(&ctx);
+ drm_atomic_state_clear(state);
+ goto retry;
+ }
+
+out:
+ if (!ret) {
+ drm_for_each_plane(plane, dev) {
+ if (plane->old_fb)
+ drm_framebuffer_unreference(plane->old_fb);
+ }
+ }
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ drm_atomic_state_put(state);
+
+ mutex_unlock(&dev->mode_config.mutex);
+}
+
+void intel_initial_mode_config_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ INIT_WORK(&dev_priv->initial_modeset_work, modeset_config_fn);
+ schedule_work(&dev_priv->initial_modeset_work);
+}
+
+static void initial_mode_destroy(struct drm_device *dev)
+{
+ struct drm_atomic_state *state;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret;
+
+ state = drm_atomic_state_alloc(dev);
+ if (!state)
+ return;
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state->acquire_ctx = &ctx;
+ drm_modeset_lock_all_ctx(dev, &ctx);
+
+retry:
+ ret = disable_planes(dev, state);
+ if (ret == -EDEADLK) {
+ drm_modeset_backoff(&ctx);
+ drm_atomic_state_clear(state);
+ goto retry;
+ }
+
+ ret = drm_atomic_commit(state);
+ if (ret == -EDEADLK) {
+ drm_modeset_backoff(&ctx);
+ drm_atomic_state_clear(state);
+ goto retry;
+ }
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
+void intel_initial_mode_config_fini(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ flush_work(&dev_priv->initial_modeset_work);
+ initial_mode_destroy(dev);
+}
--
2.17.1

92
0876-keystore-fix-memory-leaks.patch Normal file
View File

@ -0,0 +1,92 @@
From 0ddfcd8058bff94e4c738564c9b894378fad92ec Mon Sep 17 00:00:00 2001
From: Cliff Cai <cliff.cai@intel.com>
Date: Tue, 15 Jan 2019 04:47:54 +0000
Subject: [PATCH 5/9] keystore: fix memory leaks
Fix several memory leaks in the driver.
Change-Id: Ic3b0b0d4a05e9e51b4acfa198ae77abf11c91bea
Tracked-On: PKT-1674
Signed-off-by: Cliff Cai <cliff.cai@intel.com>
---
security/keystore/api_dal.c | 2 ++
security/keystore/applet_read.c | 4 +++-
security/keystore/dal_client.c | 5 ++++-
security/keystore/mac.c | 1 +
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/security/keystore/api_dal.c b/security/keystore/api_dal.c
index d97dd469d404..5db0a7ea7e10 100644
--- a/security/keystore/api_dal.c
+++ b/security/keystore/api_dal.c
@@ -803,6 +803,7 @@ int dal_keystore_encrypt(const uint8_t *client_ticket, int slot_id,
if (res) {
ks_err(KBUILD_MODNAME ": %s Error calculating client ID: %d\n",
__func__, res);
+ kzfree(in);
goto exit;
}
@@ -955,6 +956,7 @@ int dal_keystore_decrypt(const uint8_t *client_ticket, int slot_id,
if (res) {
ks_err(KBUILD_MODNAME ": %s Error calculating client ID: %d\n",
__func__, res);
+ kzfree(in);
goto exit;
}
diff --git a/security/keystore/applet_read.c b/security/keystore/applet_read.c
index 92d2a4bed416..c9640644b583 100644
--- a/security/keystore/applet_read.c
+++ b/security/keystore/applet_read.c
@@ -67,8 +67,10 @@ static int read_applet_file(struct file *file, u8 **out)
return -ENOMEM;
temp = kzalloc(i_size, GFP_KERNEL);
- if (!temp)
+ if (!temp) {
+ kzfree(file_buf);
return -ENOMEM;
+ }
if (!(file->f_mode & FMODE_READ)) {
file->f_mode |= FMODE_READ;
diff --git a/security/keystore/dal_client.c b/security/keystore/dal_client.c
index 92307502d198..b4324949bf65 100644
--- a/security/keystore/dal_client.c
+++ b/security/keystore/dal_client.c
@@ -16,6 +16,7 @@
#include <linux/dal.h>
#include <linux/printk.h>
+#include <linux/slab.h>
#include "dal_client.h"
#include "keystore_debug.h"
@@ -56,8 +57,10 @@ int install_applet(void)
dal_hdr.state = DAL_KSM_INIT;
ret = read_keystore_applet(CONFIG_DAL_KEYSTORE_APPLET_PATH, &acp_pkg,
&acp_pkg_len);
- if (ret != 0)
+ if (ret != 0) {
+ kzfree(&acp_pkg);
return ret;
+ }
if (acp_pkg == NULL) {
ks_err(KBUILD_MODNAME ": %s acp_pkg is NULL\n", __func__);
diff --git a/security/keystore/mac.c b/security/keystore/mac.c
index 4f13df6b93d4..fe6477a9f86e 100644
--- a/security/keystore/mac.c
+++ b/security/keystore/mac.c
@@ -138,6 +138,7 @@ int keystore_sha256_block(const void *data, unsigned int size,
if (result_size < crypto_shash_digestsize(tfm)) {
crypto_free_shash(tfm);
+ kzfree(sdesc);
return -EINVAL;
}
--
2.17.1

30
0877-keystore-fix-missing-break.patch Normal file
View File

@ -0,0 +1,30 @@
From 4dc9e1d63c6d5a67ac05225ff313fe8a6e03ab94 Mon Sep 17 00:00:00 2001
From: Cliff Cai <cliff.cai@intel.com>
Date: Tue, 15 Jan 2019 04:32:13 +0000
Subject: [PATCH 6/9] keystore: fix missing break
A break is needed for version case.
Change-Id: If6981607e6f3689fc0c404a54590202f5891fe02
Tracked-On: PKT-1673
Signed-off-by: Cliff Cai <cliff.cai@intel.com>
---
security/keystore/ioctls.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/security/keystore/ioctls.c b/security/keystore/ioctls.c
index e688ca9d299f..2471eb782177 100644
--- a/security/keystore/ioctls.c
+++ b/security/keystore/ioctls.c
@@ -448,6 +448,8 @@ long keystore_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
switch (cmd) {
case KEYSTORE_IOC_VERSION:
res = version_op(&op.version);
+ break;
+
case KEYSTORE_IOC_REGISTER:
res = register_op(&op.register_client_type);
break;
--
2.17.1

3742
0878-keystore-add-application-authentication-fea.patch Normal file
View File

File diff suppressed because it is too large Load Diff

234
0879-Revert-drm-i915-Add-plane-alpha-blending-su.patch Normal file
View File

@ -0,0 +1,234 @@
From e5694a1de4aca022b985c4d0c0ac05af304caf64 Mon Sep 17 00:00:00 2001
From: "Pan, Kris" <kris.pan@intel.com>
Date: Thu, 17 Jan 2019 01:02:42 -0800
Subject: [PATCH 8/9] Revert "drm/i915: Add plane alpha blending support, v2."
This reverts commit b469be4bbee273ad7e74ebcfca06acaa9b8b4e92.
It caused a regression that SOS image can't boot to GUI.
Change-Id: I913eee3b336ccb51c4776fb055b53126dc8cd230
Tracked-On: PKT-1679
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_reg.h | 2 --
drivers/gpu/drm/i915/intel_display.c | 52 +++++++++-------------------
drivers/gpu/drm/i915/intel_fbc.c | 8 -----
drivers/gpu/drm/i915/intel_sprite.c | 23 ++----------
5 files changed, 18 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fb6539653859..c0633ea208a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -558,8 +558,6 @@ struct intel_fbc {
int adjusted_y;
int y;
-
- uint16_t pixel_blend_mode;
} plane;
struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c69f6278720a..0297014630a5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,10 +6569,8 @@ enum {
#define _PLANE_KEYVAL_2_A 0x70294
#define _PLANE_KEYMSK_1_A 0x70198
#define _PLANE_KEYMSK_2_A 0x70298
-#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
-#define PLANE_KEYMAX_ALPHA_SHIFT 24
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6b368e39ea8..223cda4b380c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3183,10 +3183,6 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- /* HW only has 8 bits pixel precision, disable plane if invisible */
- if (!(plane_state->base.alpha >> 8))
- plane_state->base.visible = false;
-
if (!plane_state->base.visible)
return 0;
@@ -3532,38 +3528,29 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return 0;
}
-static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
+/*
+ * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
+ * to be already pre-multiplied. We need to add a knob (or a different
+ * DRM_FORMAT) for user-space to configure that.
+ */
+static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
{
- if (!plane_state->base.fb->format->has_alpha)
- return PLANE_CTL_ALPHA_DISABLE;
-
- switch (plane_state->base.pixel_blend_mode) {
- case DRM_MODE_BLEND_PIXEL_NONE:
- return PLANE_CTL_ALPHA_DISABLE;
- case DRM_MODE_BLEND_PREMULTI:
+ switch (pixel_format) {
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB8888:
return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
- case DRM_MODE_BLEND_COVERAGE:
- return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
default:
- MISSING_CASE(plane_state->base.pixel_blend_mode);
return PLANE_CTL_ALPHA_DISABLE;
}
}
-static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
+static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
{
- if (!plane_state->base.fb->format->has_alpha)
- return PLANE_COLOR_ALPHA_DISABLE;
-
- switch (plane_state->base.pixel_blend_mode) {
- case DRM_MODE_BLEND_PIXEL_NONE:
- return PLANE_COLOR_ALPHA_DISABLE;
- case DRM_MODE_BLEND_PREMULTI:
+ switch (pixel_format) {
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB8888:
return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
- case DRM_MODE_BLEND_COVERAGE:
- return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
default:
- MISSING_CASE(plane_state->base.pixel_blend_mode);
return PLANE_COLOR_ALPHA_DISABLE;
}
}
@@ -3640,7 +3627,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
plane_ctl = PLANE_CTL_ENABLE;
if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
- plane_ctl |= skl_plane_ctl_alpha(plane_state);
+ plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
plane_ctl |=
PLANE_CTL_PIPE_GAMMA_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3682,7 +3669,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
}
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
- plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
+ plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
if (fb->format->is_yuv) {
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
@@ -13891,7 +13878,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
DRM_ERROR("Failed to create decryption property\n");
}
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9)
drm_plane_create_color_properties(&primary->base,
BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709),
@@ -13900,13 +13887,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
- drm_plane_create_alpha_property(&primary->base);
- drm_plane_create_blend_mode_property(&primary->base,
- BIT(DRM_MODE_BLEND_PIXEL_NONE) |
- BIT(DRM_MODE_BLEND_PREMULTI) |
- BIT(DRM_MODE_BLEND_COVERAGE));
- }
-
drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
return primary;
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index c07d69f22e40..01d1d2088f04 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -674,8 +674,6 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->plane.adjusted_y = plane_state->main.y;
cache->plane.y = plane_state->base.src.y1 >> 16;
- cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
-
if (!cache->plane.visible)
return;
@@ -750,12 +748,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
- if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
- cache->fb.format->has_alpha) {
- fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
- return false;
- }
-
/* WaFbcExceedCdClockThreshold:hsw,bdw */
if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 74d594232843..2c0cc897c41e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -319,7 +319,6 @@ skl_update_plane(struct intel_plane *plane,
uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
uint32_t val;
unsigned long irqflags;
- u32 keymsk = 0, keymax = 0;
#if IS_ENABLED(CONFIG_DRM_I915_GVT)
if (dev_priv->gvt &&
@@ -346,19 +345,10 @@ skl_update_plane(struct intel_plane *plane,
if (key->flags) {
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
-
- keymax |= key->max_value & 0xffffff;
- keymsk |= key->channel_mask & 0x3ffffff;
+ I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
+ I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
}
- keymax |= (plane_state->base.alpha >> 8) << PLANE_KEYMAX_ALPHA_SHIFT;
-
- if (plane_state->base.alpha < 0xff00)
- keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
-
- I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
- I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
-
I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
@@ -1755,15 +1745,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
- if (INTEL_GEN(dev_priv) >= 9) {
- drm_plane_create_alpha_property(&intel_plane->base);
-
- drm_plane_create_blend_mode_property(&intel_plane->base,
- BIT(DRM_MODE_BLEND_PIXEL_NONE) |
- BIT(DRM_MODE_BLEND_PREMULTI) |
- BIT(DRM_MODE_BLEND_COVERAGE));
- }
-
drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
return intel_plane;
--
2.17.1

243
0880-Revert-drm-Add-per-plane-pixel-blend-mode-p.patch Normal file
View File

@ -0,0 +1,243 @@
From 56b0329e9ed204e7eb214e6b10c1d3c14a89905c Mon Sep 17 00:00:00 2001
From: "Pan, Kris" <kris.pan@intel.com>
Date: Thu, 17 Jan 2019 01:02:59 -0800
Subject: [PATCH 9/9] Revert "drm: Add per-plane pixel blend mode property"
This reverts commit 702d282a946bc51096db62f3a100f19a35e4264e.
It caused a regression that SOS image can't boot to GUI.
Change-Id: Iaf099c8176df7d7d654d32047192165f4ddb2b1d
Tracked-On: PKT-1679
---
drivers/gpu/drm/drm_atomic.c | 4 -
drivers/gpu/drm/drm_atomic_helper.c | 1 -
drivers/gpu/drm/drm_blend.c | 123 ----------------------------
include/drm/drm_blend.h | 6 --
include/drm/drm_plane.h | 9 --
5 files changed, 143 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index f2b173d07e41..d3c3c65bf5b7 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -910,8 +910,6 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane,
state->src_h = val;
} else if (property == plane->alpha_property) {
state->alpha = val;
- } else if (property == plane->blend_mode_property) {
- state->pixel_blend_mode = val;
} else if (property == plane->rotation_property) {
if (!is_power_of_2(val & DRM_MODE_ROTATE_MASK)) {
DRM_DEBUG_ATOMIC("[PLANE:%d:%s] bad rotation bitmask: 0x%llx\n",
@@ -987,8 +985,6 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = state->src_h;
} else if (property == plane->alpha_property) {
*val = state->alpha;
- } else if (property == plane->blend_mode_property) {
- *val = state->pixel_blend_mode;
} else if (property == plane->rotation_property) {
*val = state->rotation;
} else if (property == plane->zpos_property) {
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index a162880b2653..824092d90cd0 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -3586,7 +3586,6 @@ void drm_atomic_helper_plane_reset(struct drm_plane *plane)
/* Reset the alpha value to fully opaque if it matters */
if (plane->alpha_property)
plane->state->alpha = plane->alpha_property->values[1];
- plane->state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
}
}
EXPORT_SYMBOL(drm_atomic_helper_plane_reset);
diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
index e0bbd1b004a5..183a7f6488c7 100644
--- a/drivers/gpu/drm/drm_blend.c
+++ b/drivers/gpu/drm/drm_blend.c
@@ -107,52 +107,6 @@
* planes. Without this property the primary plane is always below the cursor
* plane, and ordering between all other planes is undefined.
*
- * pixel blend mode:
- * Pixel blend mode is set up with drm_plane_create_blend_mode_property().
- * It adds a blend mode for alpha blending equation selection, describing
- * how the pixels from the current plane are composited with the
- * background.
- *
- * Three alpha blending equations are defined:
- *
- * "None":
- * Blend formula that ignores the pixel alpha::
- *
- * out.rgb = plane_alpha * fg.rgb +
- * (1 - plane_alpha) * bg.rgb
- *
- * "Pre-multiplied":
- * Blend formula that assumes the pixel color values
- * have been already pre-multiplied with the alpha
- * channel values::
- *
- * out.rgb = plane_alpha * fg.rgb +
- * (1 - (plane_alpha * fg.alpha)) * bg.rgb
- *
- * "Coverage":
- * Blend formula that assumes the pixel color values have not
- * been pre-multiplied and will do so when blending them to the
- * background color values::
- *
- * out.rgb = plane_alpha * fg.alpha * fg.rgb +
- * (1 - (plane_alpha * fg.alpha)) * bg.rgb
- *
- * Using the following symbols:
- *
- * "fg.rgb":
- * Each of the RGB component values from the plane's pixel
- * "fg.alpha":
- * Alpha component value from the plane's pixel. If the plane's
- * pixel format has no alpha component, then this is assumed to be
- * 1.0. In these cases, this property has no effect, as all three
- * equations become equivalent.
- * "bg.rgb":
- * Each of the RGB component values from the background
- * "plane_alpha":
- * Plane alpha value set by the plane "alpha" property. If the
- * plane does not expose the "alpha" property, then this is
- * assumed to be 1.0
- *
* Note that all the property extensions described here apply either to the
* plane or the CRTC (e.g. for the background color, which currently is not
* exposed and assumed to be black).
@@ -526,80 +480,3 @@ int drm_atomic_normalize_zpos(struct drm_device *dev,
return 0;
}
EXPORT_SYMBOL(drm_atomic_normalize_zpos);
-
-/**
- * drm_plane_create_blend_mode_property - create a new blend mode property
- * @plane: drm plane
- * @supported_modes: bitmask of supported modes, must include
- * BIT(DRM_MODE_BLEND_PREMULTI). Current DRM assumption is
- * that alpha is premultiplied, and old userspace can break if
- * the property defaults to anything else.
- *
- * This creates a new property describing the blend mode.
- *
- * The property exposed to userspace is an enumeration property (see
- * drm_property_create_enum()) called "pixel blend mode" and has the
- * following enumeration values:
- *
- * "None":
- * Blend formula that ignores the pixel alpha.
- *
- * "Pre-multiplied":
- * Blend formula that assumes the pixel color values have been already
- * pre-multiplied with the alpha channel values.
- *
- * "Coverage":
- * Blend formula that assumes the pixel color values have not been
- * pre-multiplied and will do so when blending them to the background color
- * values.
- *
- * RETURNS:
- * Zero for success or -errno
- */
-int drm_plane_create_blend_mode_property(struct drm_plane *plane,
- unsigned int supported_modes)
-{
- struct drm_device *dev = plane->dev;
- struct drm_property *prop;
- static const struct drm_prop_enum_list props[] = {
- { DRM_MODE_BLEND_PIXEL_NONE, "None" },
- { DRM_MODE_BLEND_PREMULTI, "Pre-multiplied" },
- { DRM_MODE_BLEND_COVERAGE, "Coverage" },
- };
- unsigned int valid_mode_mask = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
- BIT(DRM_MODE_BLEND_PREMULTI) |
- BIT(DRM_MODE_BLEND_COVERAGE);
- int i;
-
- if (WARN_ON((supported_modes & ~valid_mode_mask) ||
- ((supported_modes & BIT(DRM_MODE_BLEND_PREMULTI)) == 0)))
- return -EINVAL;
-
- prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
- "pixel blend mode",
- hweight32(supported_modes));
- if (!prop)
- return -ENOMEM;
-
- for (i = 0; i < ARRAY_SIZE(props); i++) {
- int ret;
-
- if (!(BIT(props[i].type) & supported_modes))
- continue;
-
- ret = drm_property_add_enum(prop, props[i].type,
- props[i].name);
-
- if (ret) {
- drm_property_destroy(dev, prop);
-
- return ret;
- }
- }
-
- drm_object_attach_property(&plane->base, prop, DRM_MODE_BLEND_PREMULTI);
- plane->blend_mode_property = prop;
-
- return 0;
-}
-EXPORT_SYMBOL(drm_plane_create_blend_mode_property);
diff --git a/include/drm/drm_blend.h b/include/drm/drm_blend.h
index 12912656ef08..74ba3e10b3a9 100644
--- a/include/drm/drm_blend.h
+++ b/include/drm/drm_blend.h
@@ -27,10 +27,6 @@
#include <linux/ctype.h>
#include <drm/drm_mode.h>
-#define DRM_MODE_BLEND_PREMULTI 0
-#define DRM_MODE_BLEND_COVERAGE 1
-#define DRM_MODE_BLEND_PIXEL_NONE 2
-
struct drm_device;
struct drm_atomic_state;
struct drm_plane;
@@ -57,6 +53,4 @@ int drm_plane_create_zpos_immutable_property(struct drm_plane *plane,
unsigned int zpos);
int drm_atomic_normalize_zpos(struct drm_device *dev,
struct drm_atomic_state *state);
-int drm_plane_create_blend_mode_property(struct drm_plane *plane,
- unsigned int supported_modes);
#endif
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 95c550a64ee8..47d018e31bce 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -117,7 +117,6 @@ struct drm_plane_state {
* details.
*/
u16 alpha;
- uint16_t pixel_blend_mode;
/**
* @rotation:
@@ -674,14 +673,6 @@ struct drm_plane {
* drm_plane_create_rotation_property().
*/
struct drm_property *rotation_property;
- /**
- * @blend_mode_property:
- * Optional "pixel blend mode" enum property for this plane.
- * Blend mode property represents the alpha blending equation selection,
- * describing how the pixels from the current plane are composited with
- * the background.
- */
- struct drm_property *blend_mode_property;
/**
* @color_encoding_property:
--
2.17.1

3
config-iot-lts2018-sos
View File

@ -5832,6 +5832,9 @@ CONFIG_HARDENED_USERCOPY_FALLBACK=y
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_MANIFEST is not set
# CONFIG_ABL_PARAMETERS is not set
# CONFIG_ABL_CMDLINE is not set
# CONFIG_INTEGRITY is not set
#

24
linux-iot-lts2018.spec
View File

@ -17,7 +17,7 @@ Name: linux-iot-lts2018
Version: 4.19.13
# Release number is the number from PKT it consist in
# YYMMDDHHMM a 10 length number
Release: 1901141831
Release: 1901170915
License: GPL-2.0
Summary: The Linux kernel
Url: http://www.kernel.org/
@ -31,8 +31,8 @@ Source5: fragment-sos
# quilt.url: https://github.com/intel/linux-intel-quilt
# quilt.branch: 4.19/base
# quilt.tag: lts-v4.19.13-base-190114T183036Z
# config.tag: lts-v4.19.13-base-190114T183036Z
# quilt.tag: lts-v4.19.13-base-190117T091501Z
# config.tag: lts-v4.19.13-base-190117T091501Z
%define ktarget0 iot-lts2018
%define kversion0 %{version}-%{release}.%{ktarget0}
@ -920,6 +920,15 @@ Patch0868: 0868-Bug-Fix-to-fix-incorrect-osid-value.patch
Patch0869: 0869-media-intel-ipu4-VIRT-Avoid-double-close-of.patch
Patch0870: 0870-media-intel-ipu4-VIRT-Increase-the-POLL_WAI.patch
Patch0871: 0871-intel-ipu4-ici-Move-empty-list-check-into-s.patch
Patch0872: 0872-drm-Add-per-plane-pixel-blend-mode-property.patch
Patch0873: 0873-drm-i915-Add-plane-alpha-blending-support-v.patch
Patch0874: 0874-igb_avb-Fix-invalid-memory-access-after-S3-.patch
Patch0875: 0875-drm-i915-Introduce-initial-mode-setting.patch
Patch0876: 0876-keystore-fix-memory-leaks.patch
Patch0877: 0877-keystore-fix-missing-break.patch
Patch0878: 0878-keystore-add-application-authentication-fea.patch
Patch0879: 0879-Revert-drm-i915-Add-plane-alpha-blending-su.patch
Patch0880: 0880-Revert-drm-Add-per-plane-pixel-blend-mode-p.patch
#END XXXX: PK Series
# Clear Linux Series
@ -1820,6 +1829,15 @@ Linux kernel extra files
%patch0869 -p1
%patch0870 -p1
%patch0871 -p1
%patch0872 -p1
%patch0873 -p1
%patch0874 -p1
%patch0875 -p1
%patch0876 -p1
%patch0877 -p1
%patch0878 -p1
%patch0879 -p1
%patch0880 -p1
# End XXXX PK Series
# Clear Linux Series

2
release
View File

@ -1 +1 @@
1901141831
1901170915